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fhdl.ir: fix port threading code.

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whitequark 2018-12-12 13:00:50 +00:00
parent 0fac1f8d0f
commit ad9b45adcd
2 changed files with 2 additions and 2 deletions
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2
examples/alu_hier.py
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@ -56,4 +56,4 @@ class ALU:
alu = ALU(width=16)
frag = alu.get_fragment(platform=None)
# print(rtlil.convert(frag, ports=[alu.op, alu.a, alu.b, alu.o]))
print(verilog.convert(frag, ports=[alu.op, alu.a, alu.b, alu.o, alu.add.o, alu.sub.o]))
print(verilog.convert(frag, ports=[alu.op, alu.a, alu.b, alu.o]))