parent
a2241fcfdb
commit
ada1d6a603
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@ -256,8 +256,8 @@ class TemplatedPlatform(Platform):
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assert False
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def emit_design(backend):
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return {"rtlil": rtlil, "verilog": verilog}[backend].convert(fragment, name=name,
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ports=list(self.iter_ports()), missing_domain=lambda name: None)
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backend_mod = {"rtlil": rtlil, "verilog": verilog}[backend]
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return backend_mod.convert_fragment(fragment, name=name)
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def emit_commands(format):
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commands = []
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