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vendor.xilinx_{7series,spartan3_6}: specialize MultiReg.

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Vivado/ISE would otherwise infer an SRL16 from a MultiReg in some cases.
This commit is contained in:
Darrell Harmon 2019-09-20 09:13:27 -06:00 committed by whitequark
parent f2550021c3
commit af7224de5d
2 changed files with 16 additions and 0 deletions
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8
nmigen/vendor/xilinx_7series.py vendored
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@ -360,3 +360,11 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
io_IO=p_port[bit], io_IOB=n_port[bit]
)
return m
def get_multi_reg(self, multireg):
m = Module()
for i, o in zip((multireg.i, *multireg._regs), multireg._regs):
o.attrs["ASYNC_REG"] = "TRUE"
m.d[multireg._o_domain] += o.eq(i)
m.d.comb += multireg.o.eq(multireg._regs[-1])
return m

8
nmigen/vendor/xilinx_spartan_3_6.py vendored
View file

@ -411,6 +411,14 @@ class XilinxSpartan3Or6Platform(TemplatedPlatform):
)
return m
def get_multi_reg(self, multireg):
m = Module()
for i, o in zip((multireg.i, *multireg._regs), multireg._regs):
o.attrs["ASYNC_REG"] = "TRUE"
m.d[multireg._o_domain] += o.eq(i)
m.d.comb += multireg.o.eq(multireg._regs[-1])
return m
XilinxSpartan3APlatform = XilinxSpartan3Or6Platform
XilinxSpartan6Platform = XilinxSpartan3Or6Platform