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hdl.mem: use different naming for array signals.

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It looks like [] is confusing gtkwave somehow.
This commit is contained in:
whitequark 2018-12-21 12:26:49 +00:00
parent e58d9ec74d
commit af7db882c0
1 changed files with 1 additions and 1 deletions
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2
nmigen/hdl/mem.py
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@ -35,7 +35,7 @@ class Memory:
# Array of signals for simulation.
self._array = Array()
for addr, data in enumerate(self.init + [0 for _ in range(self.depth - len(self.init))]):
self._array.append(Signal(self.width, reset=data, name="{}[{}]".format(name, addr)))
self._array.append(Signal(self.width, reset=data, name="{}({})".format(name, addr)))
def read_port(self, domain="sync", synchronous=True, transparent=True):
if not synchronous and not transparent: