hdl.ast: make Value.__abs__
return unsigned shape.
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@ -263,7 +263,7 @@ class Value(metaclass=ABCMeta):
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def __abs__(self):
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if self.shape().signed:
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return Mux(self >= 0, self, -self)
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return Mux(self >= 0, self, -self)[:len(self)]
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else:
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return self
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@ -675,6 +675,17 @@ class OperatorTestCase(FHDLTestCase):
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with self.assertRaises(TypeError):
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hash(Const(0) + Const(0))
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def test_abs(self):
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s = Signal(4)
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self.assertRepr(abs(s), """
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(sig s)
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""")
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s = Signal(signed(4))
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self.assertRepr(abs(s), """
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(slice (m (>= (sig s) (const 1'd0)) (sig s) (- (sig s))) 0:4)
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""")
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self.assertEqual(abs(s).shape(), unsigned(4))
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class SliceTestCase(FHDLTestCase):
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def test_shape(self):
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