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back.rtlil: match shape of $mux ports A/B/Y.

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This commit is contained in:
whitequark 2018-12-13 02:35:46 +00:00
parent 17767642be
commit b42620e490
1 changed files with 6 additions and 3 deletions
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9
nmigen/back/rtlil.py
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@ -349,14 +349,17 @@ class _ValueTransformer(xfrm.ValueTransformer):
lhs_bits, lhs_sign = lhs.shape() lhs_bits, lhs_sign = lhs.shape()
rhs_bits, rhs_sign = rhs.shape() rhs_bits, rhs_sign = rhs.shape()
res_bits, res_sign = node.shape() res_bits, res_sign = node.shape()
lhs_bits = rhs_bits = res_bits = max(lhs_bits, rhs_bits, res_bits)
lhs_wire = self.match_shape(lhs, lhs_bits, lhs_sign)
rhs_wire = self.match_shape(rhs, rhs_bits, rhs_sign)
res = self.rtlil.wire(width=res_bits) res = self.rtlil.wire(width=res_bits)
self.rtlil.cell("$mux", ports={ self.rtlil.cell("$mux", ports={
"\\A": self(lhs), "\\A": lhs_wire,
"\\B": self(rhs), "\\B": rhs_wire,
"\\S": self(sel), "\\S": self(sel),
"\\Y": res, "\\Y": res,
}, params={ }, params={
"WIDTH": max(lhs_bits, rhs_bits, res_bits) "WIDTH": res_bits
}) })
return res return res