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Clarify a few comments. NFC.

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This commit is contained in:
whitequark 2020-04-13 13:03:31 +00:00
parent 06c45c9ff0
commit b44870e779
2 changed files with 3 additions and 6 deletions
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2
nmigen/back/rtlil.py
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@ -576,7 +576,7 @@ class _RHSValueCompiler(_ValueCompiler):
res_bits, res_sign = value.shape()
res = self.s.rtlil.wire(width=res_bits, src=src(value.src_loc))
# Note: Verilog's x[o+:w] construct produces a $shiftx cell, not a $shift cell.
# However, Migen's semantics defines the out-of-range bits to be zero, so it is correct
# However, nMigen's semantics defines the out-of-range bits to be zero, so it is correct
# to use a $shift cell here instead, even though it produces less idiomatic Verilog.
self.s.rtlil.cell("$shift", ports={
"\\A": self(lhs),

7
nmigen/build/run.py
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@ -88,11 +88,8 @@ class BuildPlan:
if run_script:
if sys.platform.startswith("win32"):
# Without "call", "cmd /c {}.bat" will return 0.
# See https://stackoverflow.com/a/30736987 for a detailed
# explanation of why, including disassembly/decompilation
# of relevant code in cmd.exe.
# Running the script manually from a command prompt is
# unaffected- i.e. "call" is not required.
# See https://stackoverflow.com/a/30736987 for a detailed explanation of why.
# Running the script manually from a command prompt is unaffected.
subprocess.check_call(["cmd", "/c", "call {}.bat".format(self.script)])
else:
subprocess.check_call(["sh", "{}.sh".format(self.script)])