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hdl.ast: support division and modulo with negative divisor.

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Fixes #621.

This commit bumps the Yosys version requirement to >=0.10.
This commit is contained in:
whitequark 2021-12-11 08:52:14 +00:00
parent 25573c5eff
commit b452e0e871
9 changed files with 41 additions and 90 deletions
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18
tests/test_hdl_ast.py
View file

@ -407,31 +407,25 @@ class OperatorTestCase(FHDLTestCase):
def test_mod(self):
v1 = Const(0, unsigned(4)) % Const(0, unsigned(6))
self.assertEqual(repr(v1), "(% (const 4'd0) (const 6'd0))")
self.assertEqual(v1.shape(), unsigned(4))
self.assertEqual(v1.shape(), unsigned(6))
v3 = Const(0, signed(4)) % Const(0, unsigned(4))
self.assertEqual(v3.shape(), signed(4))
self.assertEqual(v3.shape(), unsigned(4))
v4 = Const(0, signed(4)) % Const(0, signed(6))
self.assertEqual(v4.shape(), signed(6))
v5 = 10 % Const(0, 4)
self.assertEqual(v5.shape(), unsigned(4))
def test_mod_wrong(self):
with self.assertRaisesRegex(NotImplementedError,
r"^Division by a signed value is not supported$"):
Const(0, signed(4)) % Const(0, signed(6))
def test_floordiv(self):
v1 = Const(0, unsigned(4)) // Const(0, unsigned(6))
self.assertEqual(repr(v1), "(// (const 4'd0) (const 6'd0))")
self.assertEqual(v1.shape(), unsigned(4))
v3 = Const(0, signed(4)) // Const(0, unsigned(4))
self.assertEqual(v3.shape(), signed(4))
v4 = Const(0, signed(4)) // Const(0, signed(6))
self.assertEqual(v4.shape(), signed(5))
v5 = 10 // Const(0, 4)
self.assertEqual(v5.shape(), unsigned(4))
def test_floordiv_wrong(self):
with self.assertRaisesRegex(NotImplementedError,
r"^Division by a signed value is not supported$"):
Const(0, signed(4)) // Const(0, signed(6))
def test_and(self):
v1 = Const(0, unsigned(4)) & Const(0, unsigned(6))
self.assertEqual(repr(v1), "(& (const 4'd0) (const 6'd0))")

14
tests/test_sim.py
View file

@ -116,6 +116,13 @@ class SimulatorUnitTestCase(FHDLTestCase):
self.assertStatement(stmt, [C(2, 4), C(2, 4)], C(1, 8))
self.assertStatement(stmt, [C(7, 4), C(2, 4)], C(3, 8))
def test_floordiv_neg(self):
stmt = lambda y, a, b: y.eq(a // b)
self.assertStatement(stmt, [C(-5, 4), C( 2, 4)], C(-3, 8))
self.assertStatement(stmt, [C(-5, 4), C(-2, 4)], C( 2, 8))
self.assertStatement(stmt, [C( 5, 4), C( 2, 4)], C( 2, 8))
self.assertStatement(stmt, [C( 5, 4), C(-2, 4)], C(-3, 8))
def test_mod(self):
stmt = lambda y, a, b: y.eq(a % b)
self.assertStatement(stmt, [C(2, 4), C(0, 4)], C(0, 8))
@ -123,6 +130,13 @@ class SimulatorUnitTestCase(FHDLTestCase):
self.assertStatement(stmt, [C(2, 4), C(2, 4)], C(0, 8))
self.assertStatement(stmt, [C(7, 4), C(2, 4)], C(1, 8))
def test_mod_neg(self):
stmt = lambda y, a, b: y.eq(a % b)
self.assertStatement(stmt, [C(-5, 4), C( 3, 4)], C( 1, 8))
self.assertStatement(stmt, [C(-5, 4), C(-3, 4)], C(-2, 8))
self.assertStatement(stmt, [C( 5, 4), C( 3, 4)], C( 2, 8))
self.assertStatement(stmt, [C( 5, 4), C(-3, 4)], C(-1, 8))
def test_and(self):
stmt = lambda y, a, b: y.eq(a & b)
self.assertStatement(stmt, [C(0b1100, 4), C(0b1010, 4)], C(0b1000, 4))