hdl.ast: give Assert and Assume their own src_loc.
This helps with patterns like `Assert(fsm.ongoing("IDLE"))`, which
would otherwise point into nMigen internals.
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3 changed files with 23 additions and 34 deletions
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@ -617,7 +617,7 @@ class _StatementCompiler(xfrm.StatementVisitor):
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self.state.rtlil.cell("$assert", ports={
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"\\A": check_wire,
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"\\EN": en_wire,
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}, src=src(stmt.test.src_loc))
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}, src=src(stmt.src_loc))
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def on_Assume(self, stmt):
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self(stmt._check.eq(stmt.test))
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@ -628,7 +628,7 @@ class _StatementCompiler(xfrm.StatementVisitor):
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self.state.rtlil.cell("$assume", ports={
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"\\A": check_wire,
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"\\EN": en_wire,
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}, src=src(stmt.test.src_loc))
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}, src=src(stmt.src_loc))
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def on_Switch(self, stmt):
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self._check_rhs(stmt.test)
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