Move star imports to make from nmigen import * usable.

examples/alu.py

@@ -1,4 +1,4 @@
-from nmigen.fhdl import *
+from nmigen import *
 from nmigen.back import rtlil, verilog
 
 

examples/alu_hier.py

@@ -1,4 +1,4 @@
-from nmigen.fhdl import *
+from nmigen import *
 from nmigen.back import rtlil, verilog
 
 

examples/arst.py

@@ -1,4 +1,4 @@
-from nmigen.fhdl import *
+from nmigen import *
 from nmigen.back import rtlil, verilog
 
 

examples/cdc.py

@@ -1,6 +1,5 @@
-from nmigen.fhdl import *
+from nmigen import *
 from nmigen.back import rtlil, verilog
-from nmigen.genlib.cdc import *
 
 
 i, o = Signal(name="i"), Signal(name="o")

examples/clkdiv.py

@@ -1,4 +1,4 @@
-from nmigen.fhdl import *
+from nmigen import *
 from nmigen.back import rtlil, verilog, pysim
 
 

examples/ctrl.py

@@ -1,4 +1,4 @@
-from nmigen.fhdl import *
+from nmigen import *
 from nmigen.back import rtlil, verilog, pysim
 
 

examples/pmux.py

@@ -1,4 +1,4 @@
-from nmigen.fhdl import *
+from nmigen import *
 from nmigen.back import rtlil, verilog
 
 

nmigen/__init__.py

@@ -0,0 +1,7 @@
+from .fhdl.ast import Value, Const, Mux, Cat, Repl, Signal, ClockSignal, ResetSignal
+from .fhdl.dsl import Module
+from .fhdl.cd import ClockDomain
+from .fhdl.ir import Fragment
+from .fhdl.xfrm import ResetInserter, CEInserter
+
+from .genlib.cdc import MultiReg

nmigen/fhdl/__init__.py

@@ -1,5 +0,0 @@
-from .cd import ClockDomain
-from .ast import Value, Const, Mux, Cat, Repl, Signal, ClockSignal, ResetSignal
-from .ir import Fragment
-from .dsl import Module
-from .xfrm import ResetInserter, CEInserter