lib.memory: improve and regularize diagnostics.
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Catherine
parent
8d44ec513d
commit
b8b1e7081b
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@ -294,7 +294,7 @@ class ReadPort:
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def __init__(self, *, addr_width, shape):
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if not isinstance(addr_width, int) or addr_width < 0:
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raise TypeError(f"`addr_width` must be a non-negative int, not {addr_width!r}")
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raise TypeError(f"Address width must be a non-negative integer, not {addr_width!r}")
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self._addr_width = addr_width
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self._shape = shape
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super().__init__({
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@ -326,24 +326,27 @@ class ReadPort:
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def __init__(self, signature, *, memory, domain, transparent_for=(), path=None, src_loc_at=0):
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if not isinstance(signature, ReadPort.Signature):
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raise TypeError(f"Expected `ReadPort.Signature`, not {signature!r}")
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raise TypeError(f"Expected signature to be ReadPort.Signature, not {signature!r}")
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if memory is not None: # may be None if created via `Signature.create()`
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if not isinstance(memory, Memory):
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raise TypeError(f"Expected `Memory` or `None`, not {memory!r}")
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if signature.shape != memory.shape or Shape.cast(signature.shape) != Shape.cast(memory.shape):
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raise ValueError(f"Memory shape {memory.shape!r} doesn't match port shape {signature.shape!r}")
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raise TypeError(f"Expected memory to be Memory or None, not {memory!r}")
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if (signature.shape != memory.shape or
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Shape.cast(signature.shape) != Shape.cast(memory.shape)):
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raise ValueError(f"Memory shape {memory.shape!r} doesn't match "
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f"port shape {signature.shape!r}")
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if signature.addr_width != ceil_log2(memory.depth):
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raise ValueError(f"Memory address width {ceil_log2(memory.depth)!r} doesn't match port address width {signature.addr_width!r}")
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raise ValueError(f"Memory address width {ceil_log2(memory.depth)!r} doesn't match "
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f"port address width {signature.addr_width!r}")
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if not isinstance(domain, str):
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raise TypeError(f"Domain has to be a string, not {domain!r}")
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raise TypeError(f"Domain must be a string, not {domain!r}")
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transparent_for = tuple(transparent_for)
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for port in transparent_for:
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if not isinstance(port, WritePort):
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raise TypeError("`transparent_for` must contain only `WritePort` instances")
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raise TypeError("Transparency set must contain only WritePort instances")
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if memory is not None and port not in memory._write_ports:
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raise ValueError("Transparent write ports must belong to the same memory")
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raise ValueError("Ports in transparency set must belong to the same memory")
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if port.domain != domain:
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raise ValueError("Transparent write ports must belong to the same domain")
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raise ValueError("Ports in transparency set must belong to the same domain")
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self._signature = signature
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self._memory = memory
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self._domain = domain
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@ -420,24 +423,26 @@ class WritePort:
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def __init__(self, *, addr_width, shape, granularity=None):
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if not isinstance(addr_width, int) or addr_width < 0:
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raise TypeError(f"`addr_width` must be a non-negative int, not {addr_width!r}")
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raise TypeError(f"Address width must be a non-negative integer, not {addr_width!r}")
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self._addr_width = addr_width
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self._shape = shape
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self._granularity = granularity
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if granularity is None:
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en_width = 1
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elif not isinstance(granularity, int) or granularity < 0:
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raise TypeError(f"Granularity must be a non-negative int or None, not {granularity!r}")
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raise TypeError(f"Granularity must be a non-negative integer or None, "
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f"not {granularity!r}")
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elif not isinstance(shape, ShapeCastable):
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actual_shape = Shape.cast(shape)
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if actual_shape.signed:
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raise ValueError("Granularity cannot be specified with signed shape")
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raise ValueError("Granularity cannot be specified for a memory with "
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"a signed shape")
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elif actual_shape.width == 0:
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en_width = 0
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elif granularity == 0:
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raise ValueError("Granularity must be positive")
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elif actual_shape.width % granularity != 0:
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raise ValueError("Granularity must divide data width")
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raise ValueError("Granularity must evenly divide data width")
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else:
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en_width = actual_shape.width // granularity
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elif isinstance(shape, data.ArrayLayout):
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@ -446,11 +451,12 @@ class WritePort:
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elif granularity == 0:
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raise ValueError("Granularity must be positive")
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elif shape.length % granularity != 0:
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raise ValueError("Granularity must divide data array length")
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raise ValueError("Granularity must evenly divide data array length")
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else:
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en_width = shape.length // granularity
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else:
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raise TypeError("Granularity can only be specified for plain unsigned `Shape` or `ArrayLayout`")
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raise TypeError("Granularity can only be specified for memories whose shape "
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"is unsigned or data.ArrayLayout")
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super().__init__({
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"en": wiring.In(en_width),
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"addr": wiring.In(addr_width),
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@ -486,18 +492,21 @@ class WritePort:
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def __init__(self, signature, *, memory, domain, path=None, src_loc_at=0):
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if not isinstance(signature, WritePort.Signature):
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raise TypeError(f"Expected `WritePort.Signature`, not {signature!r}")
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raise TypeError(f"Expected signature to be WritePort.Signature, not {signature!r}")
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if memory is not None: # may be None if created via `Signature.create()`
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if not isinstance(memory, Memory):
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raise TypeError(f"Expected `Memory` or `None`, not {memory!r}")
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if signature.shape != memory.shape or Shape.cast(signature.shape) != Shape.cast(memory.shape):
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raise ValueError(f"Memory shape {memory.shape!r} doesn't match port shape {signature.shape!r}")
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raise TypeError(f"Expected memory to be Memory or None, not {memory!r}")
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if (signature.shape != memory.shape or
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Shape.cast(signature.shape) != Shape.cast(memory.shape)):
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raise ValueError(f"Memory shape {memory.shape!r} doesn't match "
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f"port shape {signature.shape!r}")
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if signature.addr_width != ceil_log2(memory.depth):
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raise ValueError(f"Memory address width {ceil_log2(memory.depth)!r} doesn't match port address width {signature.addr_width!r}")
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raise ValueError(f"Memory address width {ceil_log2(memory.depth)!r} doesn't match "
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f"port address width {signature.addr_width!r}")
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if not isinstance(domain, str):
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raise TypeError(f"Domain has to be a string, not {domain!r}")
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raise TypeError(f"Domain must be a string, not {domain!r}")
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if domain == "comb":
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raise ValueError("Write port domain cannot be \"comb\"")
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raise ValueError("Write ports cannot be asynchronous")
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self._signature = signature
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self._memory = memory
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self._domain = domain
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@ -58,28 +58,29 @@ class WritePortTestCase(FHDLTestCase):
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def test_signature_wrong(self):
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with self.assertRaisesRegex(TypeError,
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"^`addr_width` must be a non-negative int, not -2$"):
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r"^Address width must be a non-negative integer, not -2$"):
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memory.WritePort.Signature(addr_width=-2, shape=8)
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with self.assertRaisesRegex(TypeError,
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"^Granularity must be a non-negative int or None, not -2$"):
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r"^Granularity must be a non-negative integer or None, not -2$"):
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memory.WritePort.Signature(addr_width=4, shape=8, granularity=-2)
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with self.assertRaisesRegex(ValueError,
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"^Granularity cannot be specified with signed shape$"):
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r"^Granularity cannot be specified for a memory with a signed shape$"):
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memory.WritePort.Signature(addr_width=2, shape=signed(8), granularity=2)
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with self.assertRaisesRegex(TypeError,
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"^Granularity can only be specified for plain unsigned `Shape` or `ArrayLayout`$"):
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r"^Granularity can only be specified for memories whose shape is unsigned or "
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r"data.ArrayLayout$"):
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memory.WritePort.Signature(addr_width=2, shape=MyStruct, granularity=2)
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with self.assertRaisesRegex(ValueError,
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"^Granularity must be positive$"):
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r"^Granularity must be positive$"):
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memory.WritePort.Signature(addr_width=2, shape=8, granularity=0)
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with self.assertRaisesRegex(ValueError,
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"^Granularity must be positive$"):
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r"^Granularity must be positive$"):
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memory.WritePort.Signature(addr_width=2, shape=data.ArrayLayout(8, 8), granularity=0)
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with self.assertRaisesRegex(ValueError,
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"^Granularity must divide data width$"):
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r"^Granularity must evenly divide data width$"):
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memory.WritePort.Signature(addr_width=2, shape=8, granularity=3)
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with self.assertRaisesRegex(ValueError,
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"^Granularity must divide data array length$"):
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r"^Granularity must evenly divide data array length$"):
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memory.WritePort.Signature(addr_width=2, shape=data.ArrayLayout(8, 8), granularity=3)
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def test_signature_eq(self):
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@ -134,17 +135,17 @@ class WritePortTestCase(FHDLTestCase):
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def test_constructor_wrong(self):
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signature = memory.ReadPort.Signature(shape=8, addr_width=4)
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with self.assertRaisesRegex(TypeError,
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r"^Expected `WritePort.Signature`, not ReadPort.Signature\(.*\)$"):
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r"^Expected signature to be WritePort.Signature, not ReadPort.Signature\(.*\)$"):
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memory.WritePort(signature, memory=None, domain="sync")
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signature = memory.WritePort.Signature(shape=8, addr_width=4, granularity=2)
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with self.assertRaisesRegex(TypeError,
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r"^Domain has to be a string, not None$"):
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r"^Domain must be a string, not None$"):
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memory.WritePort(signature, memory=None, domain=None)
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with self.assertRaisesRegex(TypeError,
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r"^Expected `Memory` or `None`, not 'a'$"):
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r"^Expected memory to be Memory or None, not 'a'$"):
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memory.WritePort(signature, memory="a", domain="sync")
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with self.assertRaisesRegex(ValueError,
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r"^Write port domain cannot be \"comb\"$"):
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r"^Write ports cannot be asynchronous$"):
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memory.WritePort(signature, memory=None, domain="comb")
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signature = memory.WritePort.Signature(shape=8, addr_width=4)
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m = memory.Memory(depth=8, shape=8, init=[])
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@ -186,7 +187,7 @@ class ReadPortTestCase(FHDLTestCase):
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def test_signature_wrong(self):
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with self.assertRaisesRegex(TypeError,
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"^`addr_width` must be a non-negative int, not -2$"):
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"^Address width must be a non-negative integer, not -2$"):
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memory.ReadPort.Signature(addr_width=-2, shape=8)
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def test_signature_eq(self):
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@ -245,14 +246,14 @@ class ReadPortTestCase(FHDLTestCase):
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def test_constructor_wrong(self):
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signature = memory.WritePort.Signature(shape=8, addr_width=4)
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with self.assertRaisesRegex(TypeError,
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r"^Expected `ReadPort.Signature`, not WritePort.Signature\(.*\)$"):
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r"^Expected signature to be ReadPort.Signature, not WritePort.Signature\(.*\)$"):
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memory.ReadPort(signature, memory=None, domain="sync")
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signature = memory.ReadPort.Signature(shape=8, addr_width=4)
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with self.assertRaisesRegex(TypeError,
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r"^Domain has to be a string, not None$"):
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r"^Domain must be a string, not None$"):
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memory.ReadPort(signature, memory=None, domain=None)
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with self.assertRaisesRegex(TypeError,
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r"^Expected `Memory` or `None`, not 'a'$"):
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r"^Expected memory to be Memory or None, not 'a'$"):
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memory.ReadPort(signature, memory="a", domain="sync")
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signature = memory.ReadPort.Signature(shape=8, addr_width=4)
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m = memory.Memory(depth=8, shape=8, init=[])
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@ -266,15 +267,15 @@ class ReadPortTestCase(FHDLTestCase):
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m = memory.Memory(depth=16, shape=8, init=[])
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port = m.read_port()
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with self.assertRaisesRegex(TypeError,
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r"^`transparent_for` must contain only `WritePort` instances$"):
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r"^Transparency set must contain only WritePort instances$"):
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memory.ReadPort(signature, memory=m, domain="sync", transparent_for=[port])
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write_port = m.write_port()
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m2 = memory.Memory(depth=16, shape=8, init=[])
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with self.assertRaisesRegex(ValueError,
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r"^Transparent write ports must belong to the same memory$"):
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r"^Ports in transparency set must belong to the same memory$"):
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memory.ReadPort(signature, memory=m2, domain="sync", transparent_for=[write_port])
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with self.assertRaisesRegex(ValueError,
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r"^Transparent write ports must belong to the same domain$"):
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r"^Ports in transparency set must belong to the same domain$"):
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memory.ReadPort(signature, memory=m, domain="other", transparent_for=[write_port])
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