parent
a658cb2bbf
commit
b90687c988
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@ -1255,10 +1255,16 @@ class Statement:
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def __init__(self, *, src_loc_at=0):
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def __init__(self, *, src_loc_at=0):
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self.src_loc = tracer.get_src_loc(1 + src_loc_at)
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self.src_loc = tracer.get_src_loc(1 + src_loc_at)
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# TODO(nmigen-0.2): remove this
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@classmethod
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@deprecated("instead of `Statement.wrap`, use `Statement.cast`")
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def wrap(cls, obj):
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return cls.cast(obj)
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@staticmethod
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@staticmethod
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def wrap(obj):
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def cast(obj):
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if isinstance(obj, Iterable):
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if isinstance(obj, Iterable):
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return _StatementList(sum((Statement.wrap(e) for e in obj), []))
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return _StatementList(sum((Statement.cast(e) for e in obj), []))
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else:
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else:
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if isinstance(obj, Statement):
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if isinstance(obj, Statement):
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return _StatementList([obj])
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return _StatementList([obj])
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@ -1359,7 +1365,7 @@ class Switch(Statement):
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new_keys = (*new_keys, key)
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new_keys = (*new_keys, key)
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if not isinstance(stmts, Iterable):
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if not isinstance(stmts, Iterable):
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stmts = [stmts]
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stmts = [stmts]
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self.cases[new_keys] = Statement.wrap(stmts)
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self.cases[new_keys] = Statement.cast(stmts)
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if orig_keys in case_src_locs:
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if orig_keys in case_src_locs:
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self.case_src_locs[new_keys] = case_src_locs[orig_keys]
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self.case_src_locs[new_keys] = case_src_locs[orig_keys]
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@ -131,7 +131,7 @@ class Module(_ModuleBuilderRoot, Elaboratable):
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self.submodules = _ModuleBuilderSubmodules(self)
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self.submodules = _ModuleBuilderSubmodules(self)
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self.domains = _ModuleBuilderDomainSet(self)
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self.domains = _ModuleBuilderDomainSet(self)
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self._statements = Statement.wrap([])
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self._statements = Statement.cast([])
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self._ctrl_context = None
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self._ctrl_context = None
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self._ctrl_stack = []
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self._ctrl_stack = []
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@ -433,7 +433,7 @@ class Module(_ModuleBuilderRoot, Elaboratable):
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while len(self._ctrl_stack) > self.domain._depth:
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while len(self._ctrl_stack) > self.domain._depth:
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self._pop_ctrl()
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self._pop_ctrl()
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for assign in Statement.wrap(assigns):
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for assign in Statement.cast(assigns):
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if not compat_mode and not isinstance(assign, (Assign, Assert, Assume, Cover)):
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if not compat_mode and not isinstance(assign, (Assign, Assert, Assume, Cover)):
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raise SyntaxError(
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raise SyntaxError(
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"Only assignments and property checks may be appended to d.{}"
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"Only assignments and property checks may be appended to d.{}"
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@ -144,7 +144,7 @@ class Fragment:
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yield from self.domains
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yield from self.domains
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def add_statements(self, *stmts):
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def add_statements(self, *stmts):
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self.statements += Statement.wrap(stmts)
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self.statements += Statement.cast(stmts)
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def add_subfragment(self, subfragment, name=None):
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def add_subfragment(self, subfragment, name=None):
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assert isinstance(subfragment, Fragment)
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assert isinstance(subfragment, Fragment)
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@ -3,7 +3,7 @@ from collections import OrderedDict
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from functools import reduce
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from functools import reduce
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from .. import tracer
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from .. import tracer
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from ..tools import union
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from ..tools import union, deprecated
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from .ast import *
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from .ast import *
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@ -19,11 +19,17 @@ DIR_FANIN = Direction.FANIN
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class Layout:
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class Layout:
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@staticmethod
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@staticmethod
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def wrap(obj, src_loc_at=0):
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def cast(obj, *, src_loc_at=0):
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if isinstance(obj, Layout):
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if isinstance(obj, Layout):
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return obj
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return obj
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return Layout(obj, src_loc_at=1 + src_loc_at)
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return Layout(obj, src_loc_at=1 + src_loc_at)
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# TODO(nmigen-0.2): remove this
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@classmethod
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@deprecated("instead of `Layout.wrap`, use `Layout.cast`")
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def wrap(cls, obj, *, src_loc_at=0):
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return cls.cast(obj, src_loc_at=1 + src_loc_at)
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def __init__(self, fields, *, src_loc_at=0):
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def __init__(self, fields, *, src_loc_at=0):
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self.fields = OrderedDict()
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self.fields = OrderedDict()
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for field in fields:
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for field in fields:
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@ -35,7 +41,7 @@ class Layout:
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name, shape = field
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name, shape = field
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direction = DIR_NONE
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direction = DIR_NONE
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if isinstance(shape, list):
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if isinstance(shape, list):
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shape = Layout.wrap(shape)
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shape = Layout.cast(shape)
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else:
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else:
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name, shape, direction = field
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name, shape, direction = field
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if not isinstance(direction, Direction):
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if not isinstance(direction, Direction):
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@ -115,7 +121,7 @@ class Record(Value):
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return b
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return b
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return "{}__{}".format(a, b)
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return "{}__{}".format(a, b)
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self.layout = Layout.wrap(layout, src_loc_at=1 + src_loc_at)
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self.layout = Layout.cast(layout, src_loc_at=1 + src_loc_at)
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self.fields = OrderedDict()
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self.fields = OrderedDict()
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for field_name, field_shape, field_dir in self.layout:
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for field_name, field_shape, field_dir in self.layout:
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if fields is not None and field_name in fields:
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if fields is not None and field_name in fields:
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@ -13,7 +13,7 @@ class UnsignedEnum(Enum):
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class LayoutTestCase(FHDLTestCase):
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class LayoutTestCase(FHDLTestCase):
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def test_fields(self):
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def test_fields(self):
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layout = Layout.wrap([
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layout = Layout.cast([
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("cyc", 1),
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("cyc", 1),
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("data", signed(32)),
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("data", signed(32)),
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("stb", 1, DIR_FANOUT),
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("stb", 1, DIR_FANOUT),
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@ -34,7 +34,7 @@ class LayoutTestCase(FHDLTestCase):
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self.assertEqual(sublayout["b"], ((1, False), DIR_NONE))
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self.assertEqual(sublayout["b"], ((1, False), DIR_NONE))
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def test_enum_field(self):
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def test_enum_field(self):
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layout = Layout.wrap([
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layout = Layout.cast([
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("enum", UnsignedEnum),
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("enum", UnsignedEnum),
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("enum_dir", UnsignedEnum, DIR_FANOUT),
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("enum_dir", UnsignedEnum, DIR_FANOUT),
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])
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])
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@ -42,18 +42,18 @@ class LayoutTestCase(FHDLTestCase):
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self.assertEqual(layout["enum_dir"], ((2, False), DIR_FANOUT))
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self.assertEqual(layout["enum_dir"], ((2, False), DIR_FANOUT))
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def test_range_field(self):
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def test_range_field(self):
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layout = Layout.wrap([
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layout = Layout.cast([
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("range", range(0, 7)),
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("range", range(0, 7)),
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])
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])
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self.assertEqual(layout["range"], ((3, False), DIR_NONE))
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self.assertEqual(layout["range"], ((3, False), DIR_NONE))
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def test_slice_tuple(self):
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def test_slice_tuple(self):
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layout = Layout.wrap([
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layout = Layout.cast([
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("a", 1),
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("a", 1),
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("b", 2),
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("b", 2),
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("c", 3)
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("c", 3)
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])
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])
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expect = Layout.wrap([
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expect = Layout.cast([
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("a", 1),
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("a", 1),
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("c", 3)
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("c", 3)
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])
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])
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@ -63,29 +63,29 @@ class LayoutTestCase(FHDLTestCase):
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with self.assertRaises(TypeError,
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with self.assertRaises(TypeError,
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msg="Field (1,) has invalid layout: should be either (name, shape) or "
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msg="Field (1,) has invalid layout: should be either (name, shape) or "
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"(name, shape, direction)"):
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"(name, shape, direction)"):
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Layout.wrap([(1,)])
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Layout.cast([(1,)])
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def test_wrong_name(self):
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def test_wrong_name(self):
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with self.assertRaises(TypeError,
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with self.assertRaises(TypeError,
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msg="Field (1, 1) has invalid name: should be a string"):
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msg="Field (1, 1) has invalid name: should be a string"):
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Layout.wrap([(1, 1)])
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Layout.cast([(1, 1)])
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def test_wrong_name_duplicate(self):
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def test_wrong_name_duplicate(self):
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with self.assertRaises(NameError,
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with self.assertRaises(NameError,
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msg="Field ('a', 2) has a name that is already present in the layout"):
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msg="Field ('a', 2) has a name that is already present in the layout"):
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Layout.wrap([("a", 1), ("a", 2)])
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Layout.cast([("a", 1), ("a", 2)])
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def test_wrong_direction(self):
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def test_wrong_direction(self):
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with self.assertRaises(TypeError,
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with self.assertRaises(TypeError,
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msg="Field ('a', 1, 0) has invalid direction: should be a Direction "
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msg="Field ('a', 1, 0) has invalid direction: should be a Direction "
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"instance like DIR_FANIN"):
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"instance like DIR_FANIN"):
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Layout.wrap([("a", 1, 0)])
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Layout.cast([("a", 1, 0)])
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def test_wrong_shape(self):
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def test_wrong_shape(self):
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with self.assertRaises(TypeError,
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with self.assertRaises(TypeError,
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msg="Field ('a', 'x') has invalid shape: should be castable to Shape or "
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msg="Field ('a', 'x') has invalid shape: should be castable to Shape or "
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"a list of fields of a nested record"):
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"a list of fields of a nested record"):
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Layout.wrap([("a", "x")])
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Layout.cast([("a", "x")])
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class RecordTestCase(FHDLTestCase):
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class RecordTestCase(FHDLTestCase):
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@ -22,7 +22,7 @@ class SimulatorUnitTestCase(FHDLTestCase):
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stmt = stmt(osig, *isigs)
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stmt = stmt(osig, *isigs)
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frag = Fragment()
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frag = Fragment()
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frag.add_statements(stmt)
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frag.add_statements(stmt)
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for signal in flatten(s._lhs_signals() for s in Statement.wrap(stmt)):
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for signal in flatten(s._lhs_signals() for s in Statement.cast(stmt)):
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frag.add_driver(signal)
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frag.add_driver(signal)
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with Simulator(frag,
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with Simulator(frag,
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@ -20,7 +20,7 @@ __all__ = ["FHDLTestCase"]
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class FHDLTestCase(unittest.TestCase):
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class FHDLTestCase(unittest.TestCase):
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def assertRepr(self, obj, repr_str):
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def assertRepr(self, obj, repr_str):
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if isinstance(obj, list):
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if isinstance(obj, list):
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obj = Statement.wrap(obj)
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obj = Statement.cast(obj)
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def prepare_repr(repr_str):
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def prepare_repr(repr_str):
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repr_str = re.sub(r"\s+", " ", repr_str)
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repr_str = re.sub(r"\s+", " ", repr_str)
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repr_str = re.sub(r"\( (?=\()", "(", repr_str)
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repr_str = re.sub(r"\( (?=\()", "(", repr_str)
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