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fhdl, back: trace and emit source locations of values.

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This commit is contained in:
whitequark 2018-12-13 11:35:20 +00:00
parent 859c2dbcf0
commit bb04c9e0da
5 changed files with 52 additions and 28 deletions
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4
examples/cdc.py
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@ -4,6 +4,8 @@ from nmigen.genlib.cdc import *
i, o = Signal(name="i"), Signal(name="o")
frag = MultiReg(i, o).get_fragment(platform=None)
m = Module()
m.submodules += MultiReg(i, o)
frag = m.lower(platform=None)
# print(rtlil.convert(frag, ports=[i, o]))
print(verilog.convert(frag, ports=[i, o]))