fhdl, back: trace and emit source locations of values.
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parent
859c2dbcf0
commit
bb04c9e0da
5 changed files with 52 additions and 28 deletions
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@ -38,7 +38,7 @@ class _Bufferer:
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def _src(self, src):
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if src:
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self._append(" attribute \\src {}", repr(src))
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self._append(" attribute \\src \"{}\"\n", src.replace("\"", "\\\""))
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class _Builder(_Namer, _Bufferer):
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@ -70,9 +70,9 @@ class _ModuleBuilder(_Namer, _Bufferer):
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def attribute(self, name, value):
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if isinstance(value, str):
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self._append("attribute \\{} \"{}\"\n", name, value.replace("\"", "\\\""))
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self._append(" attribute \\{} \"{}\"\n", name, value.replace("\"", "\\\""))
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else:
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self._append("attribute \\{} {}\n", name, int(value))
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self._append(" attribute \\{} {}\n", name, int(value))
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def wire(self, width, port_id=None, port_kind=None, name=None, src=""):
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self._src(src)
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@ -190,6 +190,11 @@ class _SyncBuilder:
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self.rtlil._append(" update {} {}\n", lhs, rhs)
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def src(src_loc):
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file, line = src_loc
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return "{}:{}".format(file, line)
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class _ValueTransformer(xfrm.ValueTransformer):
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operator_map = {
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(1, "~"): "$not",
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@ -275,9 +280,11 @@ class _ValueTransformer(xfrm.ValueTransformer):
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for attr_name, attr_value in node.attrs.items():
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self.rtlil.attribute(attr_name, attr_value)
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wire_curr = self.rtlil.wire(width=node.nbits, name=wire_name,
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port_id=port_id, port_kind=port_kind)
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port_id=port_id, port_kind=port_kind,
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src=src(node.src_loc))
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if node in self.driven:
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wire_next = self.rtlil.wire(width=node.nbits, name=wire_curr + "$next")
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wire_next = self.rtlil.wire(width=node.nbits, name=wire_curr + "$next",
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src=src(node.src_loc))
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else:
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wire_next = None
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self.wires[node] = (wire_curr, wire_next)
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@ -301,7 +308,7 @@ class _ValueTransformer(xfrm.ValueTransformer):
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"A_SIGNED": arg_sign,
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"A_WIDTH": arg_bits,
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"Y_WIDTH": res_bits,
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})
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}, src=src(node.src_loc))
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return res
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def match_shape(self, node, new_bits, new_sign):
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@ -318,7 +325,7 @@ class _ValueTransformer(xfrm.ValueTransformer):
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"A_SIGNED": node_sign,
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"A_WIDTH": node_bits,
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"Y_WIDTH": new_bits,
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})
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}, src=src(node.src_loc))
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return res
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else:
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return "{} [{}:0]".format(self(node), new_bits - 1)
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@ -347,7 +354,7 @@ class _ValueTransformer(xfrm.ValueTransformer):
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"B_SIGNED": rhs_sign,
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"B_WIDTH": rhs_bits,
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"Y_WIDTH": res_bits,
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})
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}, src=src(node.src_loc))
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return res
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def on_Operator_mux(self, node):
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@ -366,7 +373,7 @@ class _ValueTransformer(xfrm.ValueTransformer):
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"\\Y": res,
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}, params={
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"WIDTH": res_bits
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})
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}, src=src(node.src_loc))
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return res
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def on_Operator(self, node):
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