Fix commit 8313d6e7
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8313d6e71c
commit
bb6a233626
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@ -2,7 +2,7 @@ import argparse
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from .hdl.ir import Fragment
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from .hdl.ir import Fragment
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from .back import rtlil, cxxrtl, verilog
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from .back import rtlil, cxxrtl, verilog
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from .sim import pysim
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from .sim import Simulator
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__all__ = ["main"]
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__all__ = ["main"]
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@ -67,7 +67,7 @@ def main_runner(parser, args, design, platform=None, name="top", ports=()):
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if args.action == "simulate":
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if args.action == "simulate":
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fragment = Fragment.get(design, platform)
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fragment = Fragment.get(design, platform)
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sim = pysim.Simulator(fragment)
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sim = Simulator(fragment)
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sim.add_clock(args.sync_period)
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sim.add_clock(args.sync_period)
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with sim.write_vcd(vcd_file=args.vcd_file, gtkw_file=args.gtkw_file, traces=ports):
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with sim.write_vcd(vcd_file=args.vcd_file, gtkw_file=args.gtkw_file, traces=ports):
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sim.run_until(args.sync_period * args.sync_clocks, run_passive=True)
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sim.run_until(args.sync_period * args.sync_clocks, run_passive=True)
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