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Fix commit 8313d6e7.

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This commit is contained in:
whitequark 2020-11-06 01:54:25 +00:00
parent 8313d6e71c
commit bb6a233626
1 changed files with 2 additions and 2 deletions
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4
nmigen/cli.py
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@ -2,7 +2,7 @@ import argparse
from .hdl.ir import Fragment
from .back import rtlil, cxxrtl, verilog
from .sim import pysim
from .sim import Simulator
__all__ = ["main"]
@ -67,7 +67,7 @@ def main_runner(parser, args, design, platform=None, name="top", ports=()):
if args.action == "simulate":
fragment = Fragment.get(design, platform)
sim = pysim.Simulator(fragment)
sim = Simulator(fragment)
sim.add_clock(args.sync_period)
with sim.write_vcd(vcd_file=args.vcd_file, gtkw_file=args.gtkw_file, traces=ports):
sim.run_until(args.sync_period * args.sync_clocks, run_passive=True)