Implement RFC 50: Print and string formatting.
Co-authored-by: Catherine <whitequark@whitequark.org>
This commit is contained in:
Wanda
Catherine
parent
715a8d4934
commit
bfe541a6d7
20 changed files with 1090 additions and 112 deletions
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@ -1,3 +1,5 @@
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# amaranth: UnusedPrint=no, UnusedProperty
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import warnings
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from enum import Enum, EnumMeta
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@ -329,8 +331,6 @@ class ValueTestCase(FHDLTestCase):
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r"^Cannot slice value with a value; use Value.bit_select\(\) or Value.word_select\(\) instead$"):
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Const(31)[s:s+3]
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def test_shift_left(self):
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self.assertRepr(Const(256, unsigned(9)).shift_left(0),
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"(cat (const 0'd0) (const 9'd256))")
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@ -452,6 +452,12 @@ class ValueTestCase(FHDLTestCase):
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s = Const(10).replicate(3)
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self.assertEqual(repr(s), "(cat (const 4'd10) (const 4'd10) (const 4'd10))")
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def test_format_wrong(self):
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sig = Signal()
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with self.assertRaisesRegex(TypeError,
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r"^Value \(sig sig\) cannot be converted to string."):
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f"{sig}"
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class ConstTestCase(FHDLTestCase):
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def test_shape(self):
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@ -1494,6 +1500,151 @@ class InitialTestCase(FHDLTestCase):
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self.assertEqual(i.shape(), unsigned(1))
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class FormatTestCase(FHDLTestCase):
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def test_construct(self):
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a = Signal()
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b = Signal()
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c = Signal()
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self.assertRepr(Format("abc"), "(format 'abc')")
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fmt = Format("{{abc}}")
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self.assertRepr(fmt, "(format '{{abc}}')")
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self.assertEqual(fmt._chunks, ("{abc}",))
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fmt = Format("{abc}", abc="{def}")
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self.assertRepr(fmt, "(format '{{def}}')")
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self.assertEqual(fmt._chunks, ("{def}",))
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fmt = Format("a: {a:0{b}}, b: {b}", a=13, b=4)
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self.assertRepr(fmt, "(format 'a: 0013, b: 4')")
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fmt = Format("a: {a:0{b}x}, b: {b}", a=a, b=4)
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self.assertRepr(fmt, "(format 'a: {:04x}, b: 4' (sig a))")
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fmt = Format("a: {a}, b: {b}, a: {a}", a=a, b=b)
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self.assertRepr(fmt, "(format 'a: {}, b: {}, a: {}' (sig a) (sig b) (sig a))")
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fmt = Format("a: {0}, b: {1}, a: {0}", a, b)
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self.assertRepr(fmt, "(format 'a: {}, b: {}, a: {}' (sig a) (sig b) (sig a))")
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fmt = Format("a: {}, b: {}", a, b)
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self.assertRepr(fmt, "(format 'a: {}, b: {}' (sig a) (sig b))")
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subfmt = Format("a: {:2x}, b: {:3x}", a, b)
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fmt = Format("sub: {}, c: {:4x}", subfmt, c)
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self.assertRepr(fmt, "(format 'sub: a: {:2x}, b: {:3x}, c: {:4x}' (sig a) (sig b) (sig c))")
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def test_construct_wrong(self):
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a = Signal()
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b = Signal(signed(16))
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with self.assertRaisesRegex(ValueError,
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r"^cannot switch from manual field specification to automatic field numbering$"):
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Format("{0}, {}", a, b)
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with self.assertRaisesRegex(ValueError,
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r"^cannot switch from automatic field numbering to manual field specification$"):
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Format("{}, {1}", a, b)
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with self.assertRaisesRegex(TypeError,
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r"^'ValueCastable' formatting is not supported$"):
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Format("{}", MockValueCastable(Const(0)))
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with self.assertRaisesRegex(ValueError,
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r"^Format specifiers \('s'\) cannot be used for 'Format' objects$"):
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Format("{:s}", Format(""))
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with self.assertRaisesRegex(ValueError,
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r"^format positional argument 1 was not used$"):
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Format("{}", a, b)
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with self.assertRaisesRegex(ValueError,
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r"^format keyword argument 'b' was not used$"):
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Format("{a}", a=a, b=b)
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with self.assertRaisesRegex(ValueError,
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r"^Invalid format specifier 'meow'$"):
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Format("{a:meow}", a=a)
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with self.assertRaisesRegex(ValueError,
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r"^Alignment '\^' is not supported$"):
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Format("{a:^13}", a=a)
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with self.assertRaisesRegex(ValueError,
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r"^Grouping option ',' is not supported$"):
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Format("{a:,}", a=a)
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with self.assertRaisesRegex(ValueError,
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r"^Presentation type 'n' is not supported$"):
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Format("{a:n}", a=a)
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with self.assertRaisesRegex(ValueError,
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r"^Cannot print signed value with format specifier 'c'$"):
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Format("{b:c}", b=b)
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with self.assertRaisesRegex(ValueError,
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r"^Value width must be divisible by 8 with format specifier 's'$"):
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Format("{a:s}", a=a)
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with self.assertRaisesRegex(ValueError,
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r"^Alignment '=' is not allowed with format specifier 'c'$"):
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Format("{a:=13c}", a=a)
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with self.assertRaisesRegex(ValueError,
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r"^Sign is not allowed with format specifier 'c'$"):
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Format("{a:+13c}", a=a)
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with self.assertRaisesRegex(ValueError,
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r"^Zero fill is not allowed with format specifier 'c'$"):
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Format("{a:013c}", a=a)
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with self.assertRaisesRegex(ValueError,
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r"^Alternate form is not allowed with format specifier 'c'$"):
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Format("{a:#13c}", a=a)
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with self.assertRaisesRegex(ValueError,
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r"^Cannot specify '_' with format specifier 'c'$"):
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Format("{a:_c}", a=a)
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def test_plus(self):
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a = Signal()
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b = Signal()
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fmt_a = Format("a = {};", a)
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fmt_b = Format("b = {};", b)
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fmt = fmt_a + fmt_b
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self.assertRepr(fmt, "(format 'a = {};b = {};' (sig a) (sig b))")
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self.assertEqual(fmt._chunks[2], ";b = ")
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def test_plus_wrong(self):
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with self.assertRaisesRegex(TypeError,
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r"^unsupported operand type\(s\) for \+: 'Format' and 'str'$"):
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Format("") + ""
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def test_format_wrong(self):
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fmt = Format("")
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with self.assertRaisesRegex(TypeError,
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r"^Format object .* cannot be converted to string."):
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f"{fmt}"
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class PrintTestCase(FHDLTestCase):
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def test_construct(self):
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a = Signal()
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b = Signal()
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p = Print("abc")
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self.assertRepr(p, "(print (format 'abc\\n'))")
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p = Print("abc", "def")
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self.assertRepr(p, "(print (format 'abc def\\n'))")
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p = Print("abc", b)
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self.assertRepr(p, "(print (format 'abc {}\\n' (sig b)))")
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p = Print(a, b, end="", sep=", ")
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self.assertRepr(p, "(print (format '{}, {}' (sig a) (sig b)))")
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p = Print(Format("a: {a:04x}", a=a))
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self.assertRepr(p, "(print (format 'a: {:04x}\\n' (sig a)))")
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def test_construct_wrong(self):
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with self.assertRaisesRegex(TypeError,
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r"^'sep' must be a string, not 13$"):
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Print("", sep=13)
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with self.assertRaisesRegex(TypeError,
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r"^'end' must be a string, not 13$"):
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Print("", end=13)
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class AssertTestCase(FHDLTestCase):
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def test_construct(self):
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a = Signal()
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b = Signal()
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p = Assert(a)
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self.assertRepr(p, "(assert (sig a))")
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p = Assert(a, "abc")
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self.assertRepr(p, "(assert (sig a) (format 'abc'))")
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p = Assert(a, Format("a = {}, b = {}", a, b))
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self.assertRepr(p, "(assert (sig a) (format 'a = {}, b = {}' (sig a) (sig b)))")
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def test_construct_wrong(self):
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a = Signal()
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b = Signal()
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with self.assertRaisesRegex(TypeError,
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r"^Property message must be None, str, or Format, not \(sig b\)$"):
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Assert(a, b)
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class SwitchTestCase(FHDLTestCase):
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def test_default_case(self):
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s = Switch(Const(0), {None: []})
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@ -87,7 +87,7 @@ class DSLTestCase(FHDLTestCase):
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def test_d_asgn_wrong(self):
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m = Module()
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with self.assertRaisesRegex(SyntaxError,
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r"^Only assignments and property checks may be appended to d\.sync$"):
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r"^Only assignments, prints, and property checks may be appended to d\.sync$"):
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m.d.sync += Switch(self.s1, {})
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def test_comb_wrong(self):
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@ -214,12 +214,12 @@ class FragmentPortsTestCase(FHDLTestCase):
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(cell 1 3 (~ 2.0))
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(cell 2 4 (~ 6.0))
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(cell 3 4 (assignment_list 1'd0 (1 0:1 1'd1)))
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(cell 4 4 (assert None 0.2 3.0))
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(cell 4 4 (assert 0.2 3.0 None))
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(cell 5 5 (~ 6.0))
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(cell 6 7 (~ 10.0))
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(cell 7 7 (~ 0.2))
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(cell 8 7 (assignment_list 1'd0 (1 0:1 1'd1)))
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(cell 9 7 (assert None 7.0 8.0))
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(cell 9 7 (assert 7.0 8.0 None))
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(cell 10 8 (~ 0.2))
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)
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""")
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@ -3146,6 +3146,69 @@ class SwitchTestCase(FHDLTestCase):
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)
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""")
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def test_print(self):
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m = Module()
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a = Signal(6)
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b = Signal(signed(8))
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en = Signal()
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m.domains.a = ClockDomain()
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m.domains.b = ClockDomain(async_reset=True)
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m.domains.c = ClockDomain(reset_less=True, clk_edge="neg")
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with m.If(en):
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m.d.comb += Print(a, end="")
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m.d.comb += Print(b)
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m.d.a += Print(a, b)
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m.d.b += Print(Format("values: {:02x}, {:+d}", a, b))
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m.d.c += Print("meow")
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nl = build_netlist(Fragment.get(m, None), [
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a, b, en,
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ClockSignal("a"), ResetSignal("a"),
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ClockSignal("b"), ResetSignal("b"),
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ClockSignal("c"),
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])
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self.assertRepr(nl, """
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(
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(module 0 None ('top')
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(input 'a' 0.2:8)
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(input 'b' 0.8:16)
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(input 'en' 0.16)
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(input 'a_clk' 0.17)
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(input 'a_rst' 0.18)
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(input 'b_clk' 0.19)
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(input 'b_rst' 0.20)
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(input 'c_clk' 0.21)
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)
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(cell 0 0 (top
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(input 'a' 2:8)
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(input 'b' 8:16)
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(input 'en' 16:17)
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(input 'a_clk' 17:18)
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(input 'a_rst' 18:19)
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(input 'b_clk' 19:20)
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(input 'b_rst' 20:21)
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(input 'c_clk' 21:22)
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))
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(cell 1 0 (matches 0.16 1))
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(cell 2 0 (priority_match 1 1.0))
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(cell 3 0 (assignment_list 1'd0 (2.0 0:1 1'd1)))
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(cell 4 0 (print 3.0 ((u 0.2:8 ''))))
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(cell 5 0 (assignment_list 1'd0 (2.0 0:1 1'd1)))
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(cell 6 0 (print 5.0 ((s 0.8:16 '') '\\n')))
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(cell 7 0 (matches 0.16 1))
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(cell 8 0 (priority_match 1 7.0))
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(cell 9 0 (assignment_list 1'd0 (8.0 0:1 1'd1)))
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(cell 10 0 (print 9.0 pos 0.17 ((u 0.2:8 '') ' ' (s 0.8:16 '') '\\n')))
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(cell 11 0 (matches 0.16 1))
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(cell 12 0 (priority_match 1 11.0))
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(cell 13 0 (assignment_list 1'd0 (12.0 0:1 1'd1)))
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(cell 14 0 (print 13.0 pos 0.19 ('values: ' (u 0.2:8 '02x') ', ' (s 0.8:16 '+d') '\\n')))
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(cell 15 0 (matches 0.16 1))
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(cell 16 0 (priority_match 1 15.0))
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(cell 17 0 (assignment_list 1'd0 (16.0 0:1 1'd1)))
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(cell 18 0 (print 17.0 neg 0.21 ('meow\\n')))
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)
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""")
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def test_assert(self):
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m = Module()
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i = Signal(6)
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@ -3154,11 +3217,11 @@ class SwitchTestCase(FHDLTestCase):
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m.domains.c = ClockDomain(reset_less=True, clk_edge="neg")
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with m.If(i[5]):
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m.d.comb += Assert(i[0])
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m.d.comb += Assume(i[1], name="a")
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m.d.comb += Assume(i[1], "aaa")
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m.d.a += Assert(i[2])
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m.d.b += Assume(i[3], name="b")
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m.d.c += Cover(i[4], name="c")
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m.d.comb += Cover(i, name="d")
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m.d.b += Assume(i[3], Format("value: {}", i))
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m.d.c += Cover(i[4], "c")
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m.d.comb += Cover(i, "d")
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nl = build_netlist(Fragment.get(m, None), [
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i,
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ClockSignal("a"), ResetSignal("a"),
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@ -3186,25 +3249,23 @@ class SwitchTestCase(FHDLTestCase):
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(cell 1 0 (matches 0.7 1))
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(cell 2 0 (priority_match 1 1.0))
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(cell 3 0 (assignment_list 1'd0 (2.0 0:1 1'd1)))
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(cell 4 0 (assert None 0.2 3.0))
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(cell 4 0 (assert 0.2 3.0 None))
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(cell 5 0 (assignment_list 1'd0 (2.0 0:1 1'd1)))
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(cell 6 0 (assume 'a' 0.3 5.0))
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(cell 6 0 (assume 0.3 5.0 ('aaa')))
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(cell 7 0 (b 0.2:8))
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(cell 8 0 (assignment_list 1'd0 (2.0 0:1 1'd1)))
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(cell 9 0 (cover 'd' 7.0 8.0))
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(cell 9 0 (cover 7.0 8.0 ('d')))
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(cell 10 0 (matches 0.7 1))
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(cell 11 0 (priority_match 1 10.0))
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(cell 12 0 (assignment_list 1'd0 (11.0 0:1 1'd1)))
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(cell 13 0 (assert None 0.4 12.0 pos 0.8))
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(cell 13 0 (assert 0.4 12.0 pos 0.8 None))
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(cell 14 0 (matches 0.7 1))
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(cell 15 0 (priority_match 1 14.0))
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(cell 16 0 (assignment_list 1'd0 (15.0 0:1 1'd1)))
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(cell 17 0 (assume 'b' 0.5 16.0 pos 0.10))
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(cell 17 0 (assume 0.5 16.0 pos 0.10 ('value: ' (u 0.2:8 ''))))
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(cell 18 0 (matches 0.7 1))
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(cell 19 0 (priority_match 1 18.0))
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(cell 20 0 (assignment_list 1'd0 (19.0 0:1 1'd1)))
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(cell 21 0 (cover 'c' 0.6 20.0 neg 0.12))
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(cell 21 0 (cover 0.6 20.0 neg 0.12 ('c')))
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)
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""")
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@ -1,5 +1,4 @@
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from amaranth.hdl import *
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from amaranth.asserts import *
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from amaranth.sim import *
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from amaranth.lib.coding import *
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@ -3,7 +3,7 @@
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import warnings
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from amaranth.hdl import *
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from amaranth.asserts import *
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from amaranth.asserts import Initial, AnyConst
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from amaranth.sim import *
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from amaranth.lib.fifo import *
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from amaranth.lib.memory import *
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@ -1,6 +1,8 @@
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import os
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import warnings
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from contextlib import contextmanager
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from contextlib import contextmanager, redirect_stdout
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from io import StringIO
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from textwrap import dedent
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from amaranth._utils import flatten
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from amaranth.hdl._ast import *
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@ -416,7 +418,7 @@ class SimulatorUnitTestCase(FHDLTestCase):
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class SimulatorIntegrationTestCase(FHDLTestCase):
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@contextmanager
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def assertSimulation(self, module, deadline=None):
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def assertSimulation(self, module, *, deadline=None):
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sim = Simulator(module)
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yield sim
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with sim.write_vcd("test.vcd", "test.gtkw"):
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@ -1074,6 +1076,104 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
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self.assertEqual((yield o), 1)
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sim.add_testbench(process)
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def test_print(self):
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m = Module()
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ctr = Signal(16)
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m.d.sync += ctr.eq(ctr + 1)
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with m.If(ctr % 3 == 0):
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m.d.sync += Print(Format("Counter: {ctr:03d}", ctr=ctr))
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output = StringIO()
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with redirect_stdout(output):
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with self.assertSimulation(m) as sim:
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sim.add_clock(1e-6, domain="sync")
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def process():
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yield Delay(1e-5)
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sim.add_testbench(process)
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self.assertEqual(output.getvalue(), dedent("""\
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Counter: 000
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Counter: 003
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Counter: 006
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Counter: 009
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"""))
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def test_print(self):
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def enc(s):
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return Cat(
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Const(b, 8)
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for b in s.encode()
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)
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m = Module()
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ctr = Signal(16)
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m.d.sync += ctr.eq(ctr + 1)
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msg = Signal(8 * 8)
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with m.If(ctr == 0):
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m.d.comb += msg.eq(enc("zero"))
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with m.Else():
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m.d.comb += msg.eq(enc("non-zero"))
|
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with m.If(ctr % 3 == 0):
|
||||
m.d.sync += Print(Format("Counter: {:>8s}", msg))
|
||||
output = StringIO()
|
||||
with redirect_stdout(output):
|
||||
with self.assertSimulation(m) as sim:
|
||||
sim.add_clock(1e-6, domain="sync")
|
||||
def process():
|
||||
yield Delay(1e-5)
|
||||
sim.add_testbench(process)
|
||||
self.assertEqual(output.getvalue(), dedent("""\
|
||||
Counter: zero
|
||||
Counter: non-zero
|
||||
Counter: non-zero
|
||||
Counter: non-zero
|
||||
"""))
|
||||
|
||||
def test_assert(self):
|
||||
m = Module()
|
||||
ctr = Signal(16)
|
||||
m.d.sync += ctr.eq(ctr + 1)
|
||||
m.d.sync += Assert(ctr < 4, Format("Counter too large: {}", ctr))
|
||||
with self.assertRaisesRegex(AssertionError,
|
||||
r"^Assertion violated: Counter too large: 4$"):
|
||||
with self.assertSimulation(m) as sim:
|
||||
sim.add_clock(1e-6, domain="sync")
|
||||
def process():
|
||||
yield Delay(1e-5)
|
||||
sim.add_testbench(process)
|
||||
|
||||
def test_assume(self):
|
||||
m = Module()
|
||||
ctr = Signal(16)
|
||||
m.d.sync += ctr.eq(ctr + 1)
|
||||
m.d.comb += Assume(ctr < 4)
|
||||
with self.assertRaisesRegex(AssertionError,
|
||||
r"^Assumption violated$"):
|
||||
with self.assertSimulation(m) as sim:
|
||||
sim.add_clock(1e-6, domain="sync")
|
||||
def process():
|
||||
yield Delay(1e-5)
|
||||
sim.add_testbench(process)
|
||||
|
||||
def test_cover(self):
|
||||
m = Module()
|
||||
ctr = Signal(16)
|
||||
m.d.sync += ctr.eq(ctr + 1)
|
||||
cover = Cover(ctr % 3 == 0, Format("Counter: {ctr:03d}", ctr=ctr))
|
||||
m.d.sync += cover
|
||||
m.d.sync += Cover(ctr % 3 == 1)
|
||||
output = StringIO()
|
||||
with redirect_stdout(output):
|
||||
with self.assertSimulation(m) as sim:
|
||||
sim.add_clock(1e-6, domain="sync")
|
||||
def process():
|
||||
yield Delay(1e-5)
|
||||
sim.add_testbench(process)
|
||||
self.assertRegex(output.getvalue(), dedent(r"""
|
||||
Coverage hit at .*test_sim\.py:\d+: Counter: 000
|
||||
Coverage hit at .*test_sim\.py:\d+: Counter: 003
|
||||
Coverage hit at .*test_sim\.py:\d+: Counter: 006
|
||||
Coverage hit at .*test_sim\.py:\d+: Counter: 009
|
||||
""").lstrip())
|
||||
|
||||
|
||||
class SimulatorRegressionTestCase(FHDLTestCase):
|
||||
def test_bug_325(self):
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue