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hdl.ir: when adding sync domain to a design, also add it to ports.

Browse source 
Otherwise we end up in a situation where the examples don't have
clk and rst as ports, which is not nice.

Fixes #67.
This commit is contained in:
whitequark 2019-05-15 06:44:50 +00:00
parent 39bc59c924
commit c337246fc5
2 changed files with 19 additions and 5 deletions
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8
nmigen/test/test_hdl_ir.py
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@ -573,9 +573,9 @@ class InstanceTestCase(FHDLTestCase):
def test_prepare(self):
self.setUp_cpu()
f = self.inst.prepare()
clk = f.domains["sync"].clk
sync_clk = f.domains["sync"].clk
self.assertEqual(f.ports, SignalDict([
(clk, "i"),
(sync_clk, "i"),
(self.rst, "i"),
(self.pins, "io"),
]))
@ -583,7 +583,11 @@ class InstanceTestCase(FHDLTestCase):
def test_prepare_explicit_ports(self):
self.setUp_cpu()
f = self.inst.prepare(ports=[self.rst, self.stb])
sync_clk = f.domains["sync"].clk
sync_rst = f.domains["sync"].rst
self.assertEqual(f.ports, SignalDict([
(sync_clk, "i"),
(sync_rst, "i"),
(self.rst, "i"),
(self.stb, "o"),
(self.pins, "io"),