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hdl.ir: when adding sync domain to a design, also add it to ports.

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Otherwise we end up in a situation where the examples don't have
clk and rst as ports, which is not nice.

Fixes #67.
This commit is contained in:
whitequark 2019-05-15 06:44:50 +00:00
parent 39bc59c924
commit c337246fc5
2 changed files with 19 additions and 5 deletions
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16
nmigen/hdl/ir.py
View file

@ -327,8 +327,13 @@ class Fragment:
def _propagate_domains(self, ensure_sync_exists): def _propagate_domains(self, ensure_sync_exists):
self._propagate_domains_up() self._propagate_domains_up()
if ensure_sync_exists and not self.domains: if ensure_sync_exists and not self.domains:
self.add_domains(ClockDomain("sync")) cd_sync = ClockDomain()
self.add_domains(cd_sync)
new_domains = (cd_sync,)
else:
new_domains = ()
self._propagate_domains_down() self._propagate_domains_down()
return new_domains
def _insert_domain_resets(self): def _insert_domain_resets(self):
from .xfrm import ResetInserter from .xfrm import ResetInserter
@ -479,14 +484,19 @@ class Fragment:
from .xfrm import SampleLowerer from .xfrm import SampleLowerer
fragment = SampleLowerer()(self) fragment = SampleLowerer()(self)
fragment._propagate_domains(ensure_sync_exists) new_domains = fragment._propagate_domains(ensure_sync_exists)
fragment._resolve_hierarchy_conflicts() fragment._resolve_hierarchy_conflicts()
fragment = fragment._insert_domain_resets() fragment = fragment._insert_domain_resets()
fragment = fragment._lower_domain_signals() fragment = fragment._lower_domain_signals()
if ports is None: if ports is None:
fragment._propagate_ports(ports=(), all_undef_as_ports=True) fragment._propagate_ports(ports=(), all_undef_as_ports=True)
else: else:
fragment._propagate_ports(ports=ports, all_undef_as_ports=False) new_ports = []
for cd in new_domains:
new_ports.append(cd.clk)
if cd.rst is not None:
new_ports.append(cd.rst)
fragment._propagate_ports(ports=(*ports, *new_ports), all_undef_as_ports=False)
return fragment return fragment

8
nmigen/test/test_hdl_ir.py
View file

@ -573,9 +573,9 @@ class InstanceTestCase(FHDLTestCase):
def test_prepare(self): def test_prepare(self):
self.setUp_cpu() self.setUp_cpu()
f = self.inst.prepare() f = self.inst.prepare()
clk = f.domains["sync"].clk sync_clk = f.domains["sync"].clk
self.assertEqual(f.ports, SignalDict([ self.assertEqual(f.ports, SignalDict([
(clk, "i"), (sync_clk, "i"),
(self.rst, "i"), (self.rst, "i"),
(self.pins, "io"), (self.pins, "io"),
])) ]))
@ -583,7 +583,11 @@ class InstanceTestCase(FHDLTestCase):
def test_prepare_explicit_ports(self): def test_prepare_explicit_ports(self):
self.setUp_cpu() self.setUp_cpu()
f = self.inst.prepare(ports=[self.rst, self.stb]) f = self.inst.prepare(ports=[self.rst, self.stb])
sync_clk = f.domains["sync"].clk
sync_rst = f.domains["sync"].rst
self.assertEqual(f.ports, SignalDict([ self.assertEqual(f.ports, SignalDict([
(sync_clk, "i"),
(sync_rst, "i"),
(self.rst, "i"), (self.rst, "i"),
(self.stb, "o"), (self.stb, "o"),
(self.pins, "io"), (self.pins, "io"),