hdl.mem: add tests for all error conditions.
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whitequark
parent
a061bfaa6c
commit
c49211c76a
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@ -28,16 +28,27 @@ class Memory:
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self.depth = depth
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self.init = None if init is None else list(init)
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def read_port(self, domain="sync", synchronous=False, transparent=True):
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if self.init is not None and len(self.init) > self.depth:
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raise ValueError("Memory initialization value count exceed memory depth ({} > {})"
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.format(len(self.init), self.depth))
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def read_port(self, domain="sync", synchronous=True, transparent=True):
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if not synchronous and not transparent:
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raise ValueError("Read port cannot be simultaneously asynchronous and non-transparent")
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return ReadPort(self, domain, synchronous, transparent)
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def write_port(self, domain="sync", priority=0, granularity=None):
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if granularity is None:
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granularity = self.width
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if not isinstance(granularity, int) or granularity < 0 or granularity > self.width:
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raise TypeError("Write port granularity must be a non-negative integer not greater "
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"than memory width, not '{!r}'"
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if not isinstance(granularity, int) or granularity < 0:
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raise TypeError("Write port granularity must be a non-negative integer, not '{!r}'"
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.format(granularity))
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if granularity > self.width:
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raise ValueError("Write port granularity must not be greater than memory width "
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"({} > {})"
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.format(granularity, self.width))
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if self.width // granularity * granularity != self.width:
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raise ValueError("Write port granularity must divide memory width evenly")
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return WritePort(self, domain, priority, granularity)
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@ -50,7 +61,7 @@ class ReadPort:
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self.addr = Signal(max=memory.depth)
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self.data = Signal(memory.width)
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if synchronous and transparent:
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if synchronous and not transparent:
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self.en = Signal()
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else:
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self.en = Const(1)
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@ -63,7 +74,7 @@ class ReadPort:
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p_CLK_ENABLE=self.synchronous,
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p_CLK_POLARITY=1,
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p_TRANSPARENT=self.transparent,
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i_CLK=ClockSignal(self.domain),
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i_CLK=ClockSignal(self.domain) if self.synchronous else Const(0),
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i_EN=self.en,
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i_ADDR=self.addr,
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o_DATA=self.data,
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@ -2,7 +2,7 @@ from ..hdl.cd import *
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from .tools import *
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class ClockDomainCase(FHDLTestCase):
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class ClockDomainTestCase(FHDLTestCase):
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def test_name(self):
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sync = ClockDomain()
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self.assertEqual(sync.name, "sync")
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109
nmigen/test/test_hdl_mem.py
Normal file
109
nmigen/test/test_hdl_mem.py
Normal file
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@ -0,0 +1,109 @@
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from ..hdl.ast import *
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from ..hdl.mem import *
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from .tools import *
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class MemoryTestCase(FHDLTestCase):
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def test_name(self):
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m1 = Memory(width=8, depth=4)
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self.assertEqual(m1.name, "m1")
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m2 = [Memory(width=8, depth=4)][0]
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self.assertEqual(m2.name, "$memory")
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m3 = Memory(width=8, depth=4, name="foo")
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self.assertEqual(m3.name, "foo")
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def test_geometry(self):
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m = Memory(width=8, depth=4)
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self.assertEqual(m.width, 8)
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self.assertEqual(m.depth, 4)
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def test_geometry_wrong(self):
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with self.assertRaises(TypeError,
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msg="Memory width must be a non-negative integer, not '-1'"):
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m = Memory(width=-1, depth=4)
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with self.assertRaises(TypeError,
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msg="Memory depth must be a non-negative integer, not '-1'"):
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m = Memory(width=8, depth=-1)
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def test_init(self):
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m = Memory(width=8, depth=4, init=range(4))
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self.assertEqual(m.init, [0, 1, 2, 3])
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def test_init_wrong(self):
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with self.assertRaises(ValueError,
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msg="Memory initialization value count exceed memory depth (8 > 4)"):
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m = Memory(width=8, depth=4, init=range(8))
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def test_read_port_transparent(self):
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mem = Memory(width=8, depth=4)
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rdport = mem.read_port()
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self.assertEqual(rdport.memory, mem)
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self.assertEqual(rdport.domain, "sync")
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self.assertEqual(rdport.synchronous, True)
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self.assertEqual(rdport.transparent, True)
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self.assertEqual(len(rdport.addr), 2)
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self.assertEqual(len(rdport.data), 8)
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self.assertEqual(len(rdport.en), 1)
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self.assertIsInstance(rdport.en, Const)
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self.assertEqual(rdport.en.value, 1)
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def test_read_port_non_transparent(self):
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mem = Memory(width=8, depth=4)
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rdport = mem.read_port(transparent=False)
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self.assertEqual(rdport.memory, mem)
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self.assertEqual(rdport.domain, "sync")
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self.assertEqual(rdport.synchronous, True)
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self.assertEqual(rdport.transparent, False)
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self.assertEqual(len(rdport.en), 1)
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self.assertIsInstance(rdport.en, Signal)
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def test_read_port_asynchronous(self):
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mem = Memory(width=8, depth=4)
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rdport = mem.read_port(synchronous=False)
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self.assertEqual(rdport.memory, mem)
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self.assertEqual(rdport.domain, "sync")
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self.assertEqual(rdport.synchronous, False)
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self.assertEqual(rdport.transparent, True)
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self.assertEqual(len(rdport.en), 1)
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self.assertIsInstance(rdport.en, Const)
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self.assertEqual(rdport.en.value, 1)
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def test_read_port_wrong(self):
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mem = Memory(width=8, depth=4)
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with self.assertRaises(ValueError,
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msg="Read port cannot be simultaneously asynchronous and non-transparent"):
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mem.read_port(synchronous=False, transparent=False)
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def test_write_port(self):
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mem = Memory(width=8, depth=4)
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wrport = mem.write_port()
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self.assertEqual(wrport.memory, mem)
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self.assertEqual(wrport.domain, "sync")
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self.assertEqual(wrport.priority, 0)
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self.assertEqual(wrport.granularity, 8)
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self.assertEqual(len(wrport.addr), 2)
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self.assertEqual(len(wrport.data), 8)
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self.assertEqual(len(wrport.en), 1)
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def test_write_port_granularity(self):
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mem = Memory(width=8, depth=4)
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wrport = mem.write_port(granularity=2)
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self.assertEqual(wrport.memory, mem)
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self.assertEqual(wrport.domain, "sync")
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self.assertEqual(wrport.priority, 0)
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self.assertEqual(wrport.granularity, 2)
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self.assertEqual(len(wrport.addr), 2)
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self.assertEqual(len(wrport.data), 8)
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self.assertEqual(len(wrport.en), 4)
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def test_write_port_granularity_wrong(self):
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mem = Memory(width=8, depth=4)
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with self.assertRaises(TypeError,
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msg="Write port granularity must be a non-negative integer, not '-1'"):
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mem.write_port(granularity=-1)
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with self.assertRaises(ValueError,
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msg="Write port granularity must not be greater than memory width (10 > 8)"):
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mem.write_port(granularity=10)
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with self.assertRaises(ValueError,
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msg="Write port granularity must divide memory width evenly"):
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mem.write_port(granularity=3)
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