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Typos and style fixes. NFC.

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This commit is contained in:
whitequark 2019-06-05 02:48:41 +00:00
parent 452c4b380b
commit c52cd72d3e
2 changed files with 6 additions and 6 deletions
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2
nmigen/build/plat.py
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@ -195,7 +195,7 @@ class TemplatedPlatform(Platform):
def toolchain_prepare(self, fragment, name, **kwargs): def toolchain_prepare(self, fragment, name, **kwargs):
# This notice serves a dual purpose: to explain that the file is autogenerated, # This notice serves a dual purpose: to explain that the file is autogenerated,
# and to incorporate # and to incorporate the nMigen version into generated code.
autogenerated = "Automatically generated by nMigen {}. Do not edit.".format(__version__) autogenerated = "Automatically generated by nMigen {}. Do not edit.".format(__version__)
def emit_design(backend): def emit_design(backend):

10
nmigen/vendor/lattice_ice40.py vendored
View file

@ -16,7 +16,7 @@ class LatticeICE40Platform(TemplatedPlatform):
Available overrides: Available overrides:
* ``verbose``: enables logging of informational messages to standard error. * ``verbose``: enables logging of informational messages to standard error.
* ``read_opts``: adds options for ``read`` Yosys command. * ``read_verilog_opts``: adds options for ``read_verilog`` Yosys command.
* ``synth_opts``: adds options for ``synth_ice40`` Yosys command. * ``synth_opts``: adds options for ``synth_ice40`` Yosys command.
* ``script_after_read``: inserts commands after ``read_ilang`` in Yosys script. * ``script_after_read``: inserts commands after ``read_ilang`` in Yosys script.
* ``script_after_synth``: inserts commands after ``synth_ice40`` in Yosys script. * ``script_after_synth``: inserts commands after ``synth_ice40`` in Yosys script.
@ -76,9 +76,9 @@ class LatticeICE40Platform(TemplatedPlatform):
""", """,
"{{name}}_pre_pack.py": r""" "{{name}}_pre_pack.py": r"""
# {{autogenerated}} # {{autogenerated}}
{% for port, frequency in platform.iter_clock_constraints() -%} {% for port_name, frequency in platform.iter_clock_constraints() -%}
{# Clock in MHz #} {# Clock in MHz #}
ctx.addClock("{{port}}", {{frequency/1000000}}) ctx.addClock("{{port_name}}", {{frequency/1000000}})
{% endfor%} {% endfor%}
""", """,
} }
@ -92,9 +92,9 @@ class LatticeICE40Platform(TemplatedPlatform):
""", """,
r""" r"""
{{get_tool("nextpnr-ice40")}} {{get_tool("nextpnr-ice40")}}
{{quiet("-q")}} {{quiet("--quiet")}}
{{get_override("nextpnr_opts")|default(["--placer","heap"])|join(" ")}} {{get_override("nextpnr_opts")|default(["--placer","heap"])|join(" ")}}
-l {{name}}.tim --log {{name}}.tim
{{platform._nextpnr_device_options[platform.device]}} {{platform._nextpnr_device_options[platform.device]}}
--package {{platform.package|lower}} --package {{platform.package|lower}}
--json {{name}}.json --json {{name}}.json