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vendor.lattice_{ice40,ecp5}: clean up $verilog_initial_trigger wires.

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These only matter in simulation and after conversion to Verilog.
During synthesis they cause Yosys to produce warnings:

  Warning: Wire $verilog_initial_trigger has an unprocessed 'init' attribute.
This commit is contained in:
whitequark 2020-11-06 01:31:14 +00:00
parent abbebf8efe
commit c6150d0586
2 changed files with 2 additions and 0 deletions
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1
nmigen/vendor/lattice_ecp5.py
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@ -122,6 +122,7 @@ class LatticeECP5Platform(TemplatedPlatform):
read_ilang {{file}}
{% endfor %}
read_ilang {{name}}.il
delete w:$verilog_initial_trigger
{{get_override("script_after_read")|default("# (script_after_read placeholder)")}}
synth_ecp5 {{get_override("synth_opts")|options}} -top {{name}}
{{get_override("script_after_synth")|default("# (script_after_synth placeholder)")}}

1
nmigen/vendor/lattice_ice40.py
View file

@ -124,6 +124,7 @@ class LatticeICE40Platform(TemplatedPlatform):
read_ilang {{file}}
{% endfor %}
read_ilang {{name}}.il
delete w:$verilog_initial_trigger
{{get_override("script_after_read")|default("# (script_after_read placeholder)")}}
synth_ice40 {{get_override("synth_opts")|options}} -top {{name}}
{{get_override("script_after_synth")|default("# (script_after_synth placeholder)")}}