lib.fifo: fix level on fifo full
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781a3aa767
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@ -380,8 +380,8 @@ class AsyncFIFO(Elaboratable, FIFOInterface):
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r_empty.eq(consume_r_gry == produce_r_gry),
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r_empty.eq(consume_r_gry == produce_r_gry),
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]
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]
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m.d[self._w_domain] += self.w_level.eq((produce_w_bin - consume_w_bin)[:self._ctr_bits-1])
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m.d[self._w_domain] += self.w_level.eq((produce_w_bin - consume_w_bin))
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m.d.comb += self.r_level.eq((produce_r_bin - consume_r_bin)[:self._ctr_bits-1])
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m.d.comb += self.r_level.eq((produce_r_bin - consume_r_bin))
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storage = Memory(width=self.width, depth=self.depth)
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storage = Memory(width=self.width, depth=self.depth)
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w_port = m.submodules.w_port = storage.write_port(domain=self._w_domain)
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w_port = m.submodules.w_port = storage.write_port(domain=self._w_domain)
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@ -302,4 +302,35 @@ class AsyncFIFOSimCase(FHDLTestCase):
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simulator = Simulator(fifo)
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simulator = Simulator(fifo)
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simulator.add_clock(100e-6)
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simulator.add_clock(100e-6)
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simulator.add_sync_process(testbench)
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simulator.add_sync_process(testbench)
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simulator.run()
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simulator.run()
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def check_async_fifo_level(self, fifo, fill_in, expected_level):
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write_done = Signal()
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def write_process():
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for i in range(fill_in):
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yield fifo.w_data.eq(i)
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yield fifo.w_en.eq(1)
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yield
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yield fifo.w_en.eq(0)
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yield
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yield
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self.assertEqual((yield fifo.w_level), expected_level)
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yield write_done.eq(1)
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def read_process():
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while not (yield write_done):
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yield
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self.assertEqual((yield fifo.r_level), expected_level)
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simulator = Simulator(fifo)
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simulator.add_clock(100e-6, domain="write")
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simulator.add_sync_process(write_process, domain="write")
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simulator.add_clock(50e-6, domain="read")
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simulator.add_sync_process(read_process, domain="read")
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with simulator.write_vcd("test.vcd"):
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simulator.run()
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def test_async_fifo_level_full(self):
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fifo = AsyncFIFO(width=32, depth=8, r_domain="read", w_domain="write")
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self.check_async_fifo_level(fifo, fill_in=10, expected_level=8)
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