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back.verilog: Fix strip_internal_attrs

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Fix the strip_internal_attrs parameter to verilog.convert by passing it
down the call stack as intended.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
This commit is contained in:
Alyssa Rosenzweig 2022-01-26 21:56:00 -05:00 committed by Catherine
parent c6dc08cbdd
commit c83b51db6d
1 changed files with 1 additions and 1 deletions
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amaranth/back/verilog.py
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@ -48,5 +48,5 @@ def convert(elaboratable, name="top", platform=None, ports=None, *, emit_src=Tru
warnings.warn("Implicit port determination is deprecated, specify ports explictly",
DeprecationWarning, stacklevel=2)
fragment = ir.Fragment.get(elaboratable, platform).prepare(ports=ports, **kwargs)
verilog_text, name_map = convert_fragment(fragment, name, emit_src=emit_src)
verilog_text, name_map = convert_fragment(fragment, name, emit_src=emit_src, strip_internal_attrs=strip_internal_attrs)
return verilog_text