build.{dsl,res,plat}: apply clock constraints to signals, not resources.

This adds the Clock() build DSL element, and adds a resource manager
function add_clock_constraint() that takes a Pin or a Signal.
Note that not all platforms, in particular not any nextpnr platforms
at the moment, can add constraints on arbitrary signals.

Fixes #86.

nmigen/vendor/lattice_ice40.py

@@ -76,9 +76,9 @@ class LatticeICE40Platform(TemplatedPlatform):
         """,
         "{{name}}_pre_pack.py": r"""
             # {{autogenerated}}
-            {% for port_name, frequency in platform.iter_clock_constraints() -%}
+            {% for signal, frequency in platform.iter_clock_constraints() -%}
             {# Clock in MHz #}
-            ctx.addClock("{{port_name}}", {{frequency/1000000}})
+            ctx.addClock("{{signal.name}}", {{frequency/1000000}})
             {% endfor%}
         """,
     }