test_sim: add missing add_process().

Fixes #43.
2019-03-28 17:50:14 +00:00 · 2019-03-28 17:50:14 +00:00 · c9c9307a5e
parent 23a07b955f
commit c9c9307a5e
1 changed files with 3 additions and 2 deletions
--- a/nmigen/test/test_sim.py
+++ b/nmigen/test/test_sim.py
@ -376,9 +376,10 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
        with self.assertSimulation(Module(), deadline=100e-6) as sim:
            sim.add_clock(1e-6)
            def process():
-                for _ in range(100):
-                    yield
+                for _ in range(101):
+                    yield Delay(1e-6)
                self.fail()
+            sim.add_process(process)

    def test_add_process_wrong(self):
        with self.assertSimulation(Module()) as sim: