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test_sim: add missing add_process().

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Fixes #43.
This commit is contained in:
whitequark 2019-03-28 17:50:14 +00:00
parent 23a07b955f
commit c9c9307a5e
1 changed files with 3 additions and 2 deletions
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5
nmigen/test/test_sim.py
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@ -376,9 +376,10 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
with self.assertSimulation(Module(), deadline=100e-6) as sim: with self.assertSimulation(Module(), deadline=100e-6) as sim:
sim.add_clock(1e-6) sim.add_clock(1e-6)
def process(): def process():
for _ in range(100): for _ in range(101):
yield yield Delay(1e-6)
self.fail() self.fail()
sim.add_process(process)
def test_add_process_wrong(self): def test_add_process_wrong(self):
with self.assertSimulation(Module()) as sim: with self.assertSimulation(Module()) as sim: