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sim.pysim: avoid redundant VCD updates.

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This commit properly addresses a bug introduced in 2efeb05c and then
temporarily fixed in 58f1d4bc.

Fixes #429.
This commit is contained in:
whitequark 2020-11-06 02:05:35 +00:00
parent 6e7dbe004e
commit c9fd000103
1 changed files with 11 additions and 7 deletions
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18
nmigen/sim/pysim.py
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@ -262,11 +262,13 @@ class _PySimulation(BaseSimulation):
def wait_interval(self, process, interval):
self.timeline.delay(interval, process)
def commit(self):
def commit(self, changed=None):
converged = True
for signal_state in self.pending:
if signal_state.commit():
converged = False
if changed is not None:
changed.update(self.pending)
self.pending.clear()
return converged
@ -294,6 +296,8 @@ class PySimEngine(BaseEngine):
process.reset()
def _step(self):
changed = set() if self._vcd_writers else None
# Performs the two phases of a delta cycle in a loop:
converged = False
while not converged:
@ -303,13 +307,13 @@ class PySimEngine(BaseEngine):
process.runnable = False
process.run()
for vcd_writer in self._vcd_writers:
for signal_state in self._state.pending:
vcd_writer.update(self._timeline.now,
signal_state.signal, signal_state.next)
# 2. commit: apply every queued signal change, waking up any waiting processes
converged = self._state.commit()
converged = self._state.commit(changed)
for vcd_writer in self._vcd_writers:
for signal_state in changed:
vcd_writer.update(self._timeline.now,
signal_state.signal, signal_state.curr)
def advance(self):
self._step()