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sim._pyrtl: fix miscompilation of -(Const(0b11, 2).as_signed()).

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Fixes #473.
This commit is contained in:
whitequark 2020-08-26 04:15:26 +00:00
parent 0802f943ba
commit cb81618c28
2 changed files with 9 additions and 1 deletions
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2
nmigen/sim/_pyrtl.py
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@ -116,7 +116,7 @@ class _RHSValueCompiler(_ValueCompiler):
if value.operator == "~": if value.operator == "~":
return f"(~{self(arg)})" return f"(~{self(arg)})"
if value.operator == "-": if value.operator == "-":
return f"(-{self(arg)})" return f"(-{sign(arg)})"
if value.operator == "b": if value.operator == "b":
return f"bool({mask(arg)})" return f"bool({mask(arg)})"
if value.operator == "r|": if value.operator == "r|":

8
nmigen/test/test_sim.py
View file

@ -365,6 +365,7 @@ class SimulatorUnitTestCase(FHDLTestCase):
self.assertStatement(stmt, [C(0b1000000)], C(0b0000010)) self.assertStatement(stmt, [C(0b1000000)], C(0b0000010))
self.assertStatement(stmt, [C(0b1000001)], C(0b0000110)) self.assertStatement(stmt, [C(0b1000001)], C(0b0000110))
class SimulatorIntegrationTestCase(FHDLTestCase): class SimulatorIntegrationTestCase(FHDLTestCase):
@contextmanager @contextmanager
def assertSimulation(self, module, deadline=None): def assertSimulation(self, module, deadline=None):
@ -788,3 +789,10 @@ class SimulatorRegressionTestCase(FHDLTestCase):
dut = Module() dut = Module()
dut.d.comb += Signal().eq(Repl(Const(1), 0)) dut.d.comb += Signal().eq(Repl(Const(1), 0))
Simulator(dut).run() Simulator(dut).run()
def test_bug_473(self):
sim = Simulator(Module())
def process():
self.assertEqual((yield -(Const(0b11, 2).as_signed())), 1)
sim.add_process(process)
sim.run()