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hdl.dsl: clarify error message for incorrect nesting.

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Refs #133.
This commit is contained in:
whitequark 2019-07-07 00:59:57 +00:00
parent 3388b5b085
commit cb8be4a1b0
2 changed files with 12 additions and 2 deletions
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2
nmigen/hdl/dsl.py
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@ -133,7 +133,7 @@ class Module(_ModuleBuilderRoot, Elaboratable):
raise SyntaxError("{} is not permitted outside of {}" raise SyntaxError("{} is not permitted outside of {}"
.format(construct, context)) .format(construct, context))
else: else:
raise SyntaxError("{} is not permitted inside of {}" raise SyntaxError("{} is not permitted directly inside of {}"
.format(construct, self._ctrl_context)) .format(construct, self._ctrl_context))
def _get_ctrl(self, name): def _get_ctrl(self, name):

12
nmigen/test/test_hdl_dsl.py
View file

@ -345,7 +345,7 @@ class DSLTestCase(FHDLTestCase):
m = Module() m = Module()
with m.Switch(self.s1): with m.Switch(self.s1):
with self.assertRaises(SyntaxError, with self.assertRaises(SyntaxError,
msg="If is not permitted inside of Switch"): msg="If is not permitted directly inside of Switch"):
with m.If(self.s2): with m.If(self.s2):
pass pass
@ -480,6 +480,16 @@ class DSLTestCase(FHDLTestCase):
with m.FSM(): with m.FSM():
m.next = "FOO" m.next = "FOO"
def test_If_inside_FSM_wrong(self):
m = Module()
with m.FSM():
with m.State("FOO"):
pass
with self.assertRaises(SyntaxError,
msg="If is not permitted directly inside of FSM"):
with m.If(self.s2):
pass
def test_auto_pop_ctrl(self): def test_auto_pop_ctrl(self):
m = Module() m = Module()
with m.If(self.w1): with m.If(self.w1):