back.pysim: explain how delta cycles work.
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whitequark
parent
e4d08d2855
commit
cb998d891b
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@ -184,9 +184,11 @@ class _StatementCompiler(StatementTransformer):
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class Simulator:
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def __init__(self, fragment=None, vcd_file=None):
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self._fragments = {} # fragment -> hierarchy
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self._domains = {} # str/domain -> ClockDomain
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self._domain_triggers = ValueDict() # Signal -> str/domain
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self._domain_signals = {} # str/domain -> {Signal}
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self._signals = ValueSet() # {Signal}
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self._comb_signals = ValueSet() # {Signal}
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self._sync_signals = ValueSet() # {Signal}
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@ -194,6 +196,7 @@ class Simulator:
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self._started = False
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self._timestamp = 0.
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self._epsilon = 1e-10
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self._state = _State()
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self._processes = set() # {process}
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@ -202,7 +205,7 @@ class Simulator:
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self._wait_deadline = {} # process -> float/timestamp
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self._wait_tick = {} # process -> str/domain
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self._handlers = ValueDict() # Signal -> set(lambda)
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self._funclets = ValueDict() # Signal -> set(lambda)
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self._vcd_file = vcd_file
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self._vcd_writer = None
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@ -255,10 +258,10 @@ class Simulator:
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return "{}_{}".format(name, signal.name)
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return signal.name
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def _add_handler(self, signal, handler):
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if signal not in self._handlers:
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self._handlers[signal] = set()
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self._handlers[signal].add(handler)
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def _add_funclet(self, signal, funclet):
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if signal not in self._funclets:
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self._funclets[signal] = set()
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self._funclets[signal].add(funclet)
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def __enter__(self):
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if self._vcd_file:
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@ -298,51 +301,92 @@ class Simulator:
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self._domain_signals[domain].update(signals)
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compiler = _StatementCompiler()
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handler = compiler(fragment.statements)
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funclet = compiler(fragment.statements)
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for signal in compiler.sensitivity:
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self._add_handler(signal, handler)
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self._add_funclet(signal, funclet)
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for domain, cd in fragment.domains.items():
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self._add_handler(cd.clk, handler)
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self._add_funclet(cd.clk, funclet)
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if cd.rst is not None:
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self._add_handler(cd.rst, handler)
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self._add_funclet(cd.rst, funclet)
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self._user_signals = self._signals - self._comb_signals - self._sync_signals
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def _commit_signal(self, signal):
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old, new = self._state.commit(signal)
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if (old, new) == (0, 1) and signal in self._domain_triggers:
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domain = self._domain_triggers[signal]
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for sync_signal in self._state.next_dirty:
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if sync_signal in self._domain_signals[domain]:
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self._commit_signal(sync_signal)
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for proc, wait_domain in list(self._wait_tick.items()):
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if domain == wait_domain:
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del self._wait_tick[proc]
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self._suspended.remove(proc)
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if self._vcd_writer:
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for vcd_signal in self._vcd_signals[signal]:
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self._vcd_writer.change(vcd_signal, self._timestamp * 1e10, new)
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def _handle_event(self):
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handlers = set()
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def _update_dirty_signals(self):
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"""Perform the statement part of IR processes (aka RTLIL case)."""
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# First, for all dirty signals, use sensitivity lists to determine the set of fragments
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# that need their statements to be reevaluated because the signals changed at the previous
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# delta cycle.
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funclets = set()
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while self._state.curr_dirty:
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signal = self._state.curr_dirty.pop()
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if signal in self._handlers:
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handlers.update(self._handlers[signal])
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if signal in self._funclets:
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funclets.update(self._funclets[signal])
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for handler in handlers:
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handler(self._state)
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# Second, compute the values of all signals at the start of the next delta cycle, by
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# running precompiled statements.
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for funclet in funclets:
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funclet(self._state)
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def _commit_signal(self, signal, domains):
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"""Perform the driver part of IR processes (aka RTLIL sync), for individual signals."""
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# Take the computed value (at the start of this delta cycle) of a signal (that could have
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# come from an IR process that ran earlier, or modified by a simulator process) and update
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# the value for this delta cycle.
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old, new = self._state.commit(signal)
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# If the signal is a clock that triggers synchronous logic, record that fact.
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if (old, new) == (0, 1) and signal in self._domain_triggers:
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domains.add(self._domain_triggers[signal])
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if self._vcd_writer:
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# Finally, dump the new value to the VCD file.
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for vcd_signal in self._vcd_signals[signal]:
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self._vcd_writer.change(vcd_signal, self._timestamp / self._epsilon, new)
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def _commit_comb_signals(self, domains):
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"""Perform the comb part of IR processes (aka RTLIL always)."""
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# Take the computed value (at the start of this delta cycle) of every comb signal and
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# update the value for this delta cycle.
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for signal in self._state.next_dirty:
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if signal in self._comb_signals or signal in self._user_signals:
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self._commit_signal(signal)
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self._commit_signal(signal, domains)
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def _commit_sync_signals(self, domains):
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"""Perform the sync part of IR processes (aka RTLIL posedge)."""
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# At entry, `domains` contains a list of every simultaneously triggered sync update.
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while domains:
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# Advance the timeline a bit (purely for observational purposes) and commit all of them
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# at the same timestamp.
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self._timestamp += self._epsilon
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curr_domains, domains = domains, set()
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while curr_domains:
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domain = curr_domains.pop()
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# Take the computed value (at the start of this delta cycle) of every sync signal
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# in this domain and update the value for this delta cycle. This can trigger more
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# synchronous logic, so record that.
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for signal in self._state.next_dirty:
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if signal in self._domain_signals[domain]:
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self._commit_signal(signal, domains)
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# Wake up any simulator processes that wait for a domain tick.
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for proc, wait_domain in list(self._wait_tick.items()):
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if domain == wait_domain:
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del self._wait_tick[proc]
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self._suspended.remove(proc)
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# Unless handling synchronous logic above has triggered more synchronous logic (which
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# can happen e.g. if a domain is clocked off a clock divisor in fabric), we're done.
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# Otherwise, do one more round of updates.
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def _force_signal(self, signal, value):
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assert signal in self._user_signals
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self._state.set_next(signal, value)
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self._commit_signal(signal)
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domains = set()
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self._commit_signal(signal, domains)
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self._commit_sync_signals(domains)
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def _run_process(self, proc):
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try:
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@ -371,8 +415,12 @@ class Simulator:
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def step(self, run_passive=False):
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# Are there any delta cycles we should run?
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while self._state.curr_dirty:
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self._timestamp += 1e-10
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self._handle_event()
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self._timestamp += self._epsilon
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domains = set()
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self._update_dirty_signals()
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self._commit_comb_signals(domains)
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self._commit_sync_signals(domains)
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# Are there any processes that haven't had a chance to run yet?
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if len(self._processes) > len(self._suspended):
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@ -400,8 +448,9 @@ class Simulator:
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while self._timestamp < deadline:
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if not self.step(run_passive):
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return False
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return True
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def __exit__(self, *args):
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if self._vcd_writer:
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self._vcd_writer.close(self._timestamp * 1e10)
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self._vcd_writer.close(self._timestamp / self._epsilon)
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