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back.pysim: handle non-driven, non-port signals.

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Fixes #20.
This commit is contained in:
whitequark 2019-01-13 08:31:38 +00:00
parent 06faeee357
commit cbf7bd6e31
2 changed files with 19 additions and 1 deletions
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14
nmigen/test/test_sim.py
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@ -531,6 +531,20 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
sim.add_clock(1e-6)
sim.add_process(process)
def test_memory_read_only(self):
self.m = Module()
self.memory = Memory(width=8, depth=4, init=[0xaa, 0x55])
self.m.submodules.rdport = self.rdport = self.memory.read_port()
with self.assertSimulation(self.m) as sim:
def process():
self.assertEqual((yield self.rdport.data), 0xaa)
yield self.rdport.addr.eq(1)
yield
yield
self.assertEqual((yield self.rdport.data), 0x55)
sim.add_clock(1e-6)
sim.add_sync_process(process)
def test_wrong_not_run(self):
with self.assertWarns(UserWarning,
msg="Simulation created, but not run"):