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back.pysim: handle non-driven, non-port signals.

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Fixes #20.
This commit is contained in:
whitequark 2019-01-13 08:31:38 +00:00
parent 06faeee357
commit cbf7bd6e31
2 changed files with 19 additions and 1 deletions
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6
nmigen/back/pysim.py
View file

@ -90,6 +90,9 @@ class _RHSValueCompiler(_ValueCompiler):
def on_Signal(self, value): def on_Signal(self, value):
if self.sensitivity is not None: if self.sensitivity is not None:
self.sensitivity.add(value) self.sensitivity.add(value)
if value not in self.signal_slots:
# A signal that is neither driven nor a port always remains at its reset state.
return lambda state: value.reset
value_slot = self.signal_slots[value] value_slot = self.signal_slots[value]
if self.signal_mode == "rhs": if self.signal_mode == "rhs":
return lambda state: state.curr[value_slot] return lambda state: state.curr[value_slot]
@ -551,7 +554,8 @@ class Simulator:
funclet = compiler(statements) funclet = compiler(statements)
def add_funclet(signal, funclet): def add_funclet(signal, funclet):
self._funclets[self._signal_slots[signal]].add(funclet) if signal in self._signal_slots:
self._funclets[self._signal_slots[signal]].add(funclet)
for signal in compiler.sensitivity: for signal in compiler.sensitivity:
add_funclet(signal, funclet) add_funclet(signal, funclet)

14
nmigen/test/test_sim.py
View file

@ -531,6 +531,20 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
sim.add_clock(1e-6) sim.add_clock(1e-6)
sim.add_process(process) sim.add_process(process)
def test_memory_read_only(self):
self.m = Module()
self.memory = Memory(width=8, depth=4, init=[0xaa, 0x55])
self.m.submodules.rdport = self.rdport = self.memory.read_port()
with self.assertSimulation(self.m) as sim:
def process():
self.assertEqual((yield self.rdport.data), 0xaa)
yield self.rdport.addr.eq(1)
yield
yield
self.assertEqual((yield self.rdport.data), 0x55)
sim.add_clock(1e-6)
sim.add_sync_process(process)
def test_wrong_not_run(self): def test_wrong_not_run(self):
with self.assertWarns(UserWarning, with self.assertWarns(UserWarning,
msg="Simulation created, but not run"): msg="Simulation created, but not run"):