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hdl.{_ast,_dsl}: factor out the pattern normalization logic.

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Wanda 2024-04-02 22:20:13 +02:00 • committed by Catherine
parent 0e4c2de725
commit cd6cbd71ca
7 changed files with 69 additions and 97 deletions
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18
tests/test_hdl_ast.py
View file

@ -795,7 +795,7 @@ class OperatorTestCase(FHDLTestCase):
def test_matches_enum(self):
s = Signal(SignedEnum)
self.assertRepr(s.matches(SignedEnum.FOO), """
(== (sig s) (const 2'sd-1))
(== (sig s) (const 1'sd-1))
""")
def test_matches_const_castable(self):
@ -807,28 +807,28 @@ class OperatorTestCase(FHDLTestCase):
def test_matches_width_wrong(self):
s = Signal(4)
with self.assertRaisesRegex(SyntaxError,
r"^Match pattern '--' must have the same width as match value \(which is 4\)$"):
r"^Pattern '--' must have the same width as match value \(which is 4\)$"):
s.matches("--")
with self.assertWarnsRegex(SyntaxWarning,
r"^Match pattern '22' \(5'10110\) is wider than match value \(which has "
r"width 4\); comparison will never be true$"):
r"^Pattern '22' \(5'10110\) is not representable in match value shape "
r"\(unsigned\(4\)\); comparison will never be true$"):
s.matches(0b10110)
with self.assertWarnsRegex(SyntaxWarning,
r"^Match pattern '\(cat \(const 1'd0\) \(const 4'd11\)\)' \(5'10110\) is wider "
r"than match value \(which has width 4\); comparison will never be true$"):
r"^Pattern '\(cat \(const 1'd0\) \(const 4'd11\)\)' \(5'10110\) is not "
r"representable in match value shape \(unsigned\(4\)\); comparison will never be true$"):
s.matches(Cat(0, C(0b1011, 4)))
def test_matches_bits_wrong(self):
s = Signal(4)
with self.assertRaisesRegex(SyntaxError,
r"^Match pattern 'abc' must consist of 0, 1, and - \(don't care\) bits, "
r"^Pattern 'abc' must consist of 0, 1, and - \(don't care\) bits, "
r"and may include whitespace$"):
s.matches("abc")
def test_matches_pattern_wrong(self):
s = Signal(4)
with self.assertRaisesRegex(SyntaxError,
r"^Match pattern must be a string or a constant-castable expression, not 1\.0$"):
r"^Pattern must be a string or a constant-castable expression, not 1\.0$"):
s.matches(1.0)
def test_hash(self):
@ -1695,7 +1695,7 @@ class SwitchTestCase(FHDLTestCase):
self.assertEqual(s.cases, {("00001010",): []})
def test_int_neg_case(self):
s = Switch(Const(0, 8), {-10: []})
s = Switch(Const(0, signed(8)), {-10: []})
self.assertEqual(s.cases, {("11110110",): []})
def test_int_zero_width(self):

14
tests/test_hdl_dsl.py
View file

@ -487,17 +487,17 @@ class DSLTestCase(FHDLTestCase):
dummy = Signal()
with m.Switch(self.w1):
with self.assertRaisesRegex(SyntaxError,
r"^Case pattern '--' must have the same width as switch value \(which is 4\)$"):
r"^Pattern '--' must have the same width as match value \(which is 4\)$"):
with m.Case("--"):
m.d.comb += dummy.eq(0)
with self.assertWarnsRegex(SyntaxWarning,
r"^Case pattern '22' \(5'10110\) is wider than switch value \(which has "
r"width 4\); comparison will never be true$"):
r"^Pattern '22' \(5'10110\) is not representable in match value shape "
r"\(unsigned\(4\)\); comparison will never be true$"):
with m.Case(0b10110):
m.d.comb += dummy.eq(0)
with self.assertWarnsRegex(SyntaxWarning,
r"^Case pattern '<Color.RED: 170>' \(8'10101010\) is wider than switch value "
r"\(which has width 4\); comparison will never be true$"):
r"^Pattern '<Color.RED: 170>' \(8'10101010\) is not representable in "
r"match value shape \(unsigned\(4\)\); comparison will never be true$"):
with m.Case(Color.RED):
m.d.comb += dummy.eq(0)
self.assertEqual(m._statements, {})
@ -521,7 +521,7 @@ class DSLTestCase(FHDLTestCase):
m = Module()
with m.Switch(self.w1):
with self.assertRaisesRegex(SyntaxError,
(r"^Case pattern 'abc' must consist of 0, 1, and - \(don't care\) bits, "
(r"^Pattern 'abc' must consist of 0, 1, and - \(don't care\) bits, "
r"and may include whitespace$")):
with m.Case("abc"):
pass
@ -530,7 +530,7 @@ class DSLTestCase(FHDLTestCase):
m = Module()
with m.Switch(self.w1):
with self.assertRaisesRegex(SyntaxError,
r"^Case pattern must be a string or a constant-castable expression, "
r"^Pattern must be a string or a constant-castable expression, "
r"not 1\.0$"):
with m.Case(1.0):
pass

1
tests/test_lib_enum.py
View file

@ -4,6 +4,7 @@ import sys
import unittest
from amaranth import *
from amaranth.hdl import *
from amaranth.lib.enum import Enum, EnumMeta, Flag, IntEnum, EnumView, FlagView
from .utils import *