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back.rtlil: fix typo.

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whitequark 2018-12-31 03:37:38 +00:00
parent 39eb2e8fa7
commit cdc40eaa9b
1 changed files with 1 additions and 1 deletions
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2
nmigen/back/rtlil.py
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@ -557,7 +557,7 @@ class _StatementCompiler(xfrm.StatementVisitor):
else:
# In RTLIL, LHS and RHS of assignment must have exactly same width.
rhs_sigspec = self.rhs_compiler.match_shape(
stmt.rhs, lhs_bits, rhs_sign)
stmt.rhs, lhs_bits, lhs_sign)
self._case.assign(self.lhs_compiler(stmt.lhs), rhs_sigspec)
def on_Switch(self, stmt):