build.{plat,res}: post-lib.io cleanup.
This commit is contained in:
Wanda
Catherine
parent
7fe62f810b
commit
cf534489a2
3 changed files with 179 additions and 272 deletions
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@ -142,34 +142,15 @@ class Platform(ResourceManager, metaclass=ABCMeta):
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def missing_domain_error(name):
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raise RuntimeError("Missing domain in pin fragment")
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def add_pin_fragment(pin, pin_fragment):
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pin_fragment = Fragment.get(pin_fragment, self)
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pin_fragment._propagate_domains(missing_domain_error)
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pin_fragment = DomainLowerer()(pin_fragment)
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fragment.add_subfragment(pin_fragment, name=f"pin_{pin.name}")
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for pin, port, buffer in self.iter_pins():
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buffer = Fragment.get(buffer, self)
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buffer._propagate_domains(missing_domain_error)
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buffer = DomainLowerer()(buffer)
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fragment.add_subfragment(buffer, name=f"pin_{pin.name}")
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for pin, port, attrs, invert in self.iter_single_ended_pins():
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if pin.dir == "i":
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add_pin_fragment(pin, self.get_input(pin, port, attrs, invert))
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if pin.dir == "o":
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add_pin_fragment(pin, self.get_output(pin, port, attrs, invert))
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if pin.dir == "oe":
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add_pin_fragment(pin, self.get_tristate(pin, port, attrs, invert))
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if pin.dir == "io":
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add_pin_fragment(pin, self.get_input_output(pin, port, attrs, invert))
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for pin, port, attrs, invert in self.iter_differential_pins():
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if pin.dir == "i":
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add_pin_fragment(pin, self.get_diff_input(pin, port, attrs, invert))
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if pin.dir == "o":
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add_pin_fragment(pin, self.get_diff_output(pin, port, attrs, invert))
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if pin.dir == "oe":
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add_pin_fragment(pin, self.get_diff_tristate(pin, port, attrs, invert))
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if pin.dir == "io":
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add_pin_fragment(pin, self.get_diff_input_output(pin, port, attrs, invert))
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fragment = Design(fragment, [], hierarchy=(name,))
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return self.toolchain_prepare(fragment, name, **kwargs)
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ports = [(port.name, port, None) for port in self.iter_ports()]
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design = Design(fragment, ports, hierarchy=(name,))
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return self.toolchain_prepare(design, name, **kwargs)
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@abstractmethod
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def toolchain_prepare(self, fragment, name, **kwargs):
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@ -186,108 +167,6 @@ class Platform(ResourceManager, metaclass=ABCMeta):
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raise NotImplementedError("Platform '{}' does not support programming"
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.format(type(self).__name__))
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def _check_feature(self, feature, pin, attrs, valid_xdrs, valid_attrs):
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if len(valid_xdrs) == 0:
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raise NotImplementedError("Platform '{}' does not support {}"
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.format(type(self).__name__, feature))
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elif pin.xdr not in valid_xdrs:
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raise NotImplementedError("Platform '{}' does not support {} for XDR {}"
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.format(type(self).__name__, feature, pin.xdr))
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if not valid_attrs and attrs:
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raise NotImplementedError("Platform '{}' does not support attributes for {}"
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.format(type(self).__name__, feature))
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@staticmethod
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def _invert_if(invert, value):
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if invert:
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return ~value
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else:
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return value
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def get_input(self, pin, port, attrs, invert):
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self._check_feature("input", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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if pin.xdr == 0:
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m.submodules.buf = buf = io.Buffer(io.Direction.Input, port)
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m.d.comb += pin.i.eq(buf.i)
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elif pin.xdr == 1:
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m.domains.input = cd_input = ClockDomain(reset_less=True)
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m.submodules.buf = buf = io.FFBuffer(io.Direction.Input, port, i_domain="input")
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m.d.comb += pin.i.eq(buf.i)
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m.d.comb += cd_input.clk.eq(pin.i_clk)
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elif pin.xdr == 2:
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m.domains.input = cd_input = ClockDomain(reset_less=True)
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m.submodules.buf = buf = io.DDRBuffer(io.Direction.Input, port, i_domain="input")
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m.d.comb += pin.i0.eq(buf.i[0])
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m.d.comb += pin.i1.eq(buf.i[1])
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m.d.comb += cd_input.clk.eq(pin.i_clk)
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return m
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def get_output(self, pin, port, attrs, invert):
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self._check_feature("output", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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if pin.xdr == 0:
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m.submodules.buf = buf = io.Buffer(io.Direction.Output, port)
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m.d.comb += buf.o.eq(pin.o)
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elif pin.xdr == 1:
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m.domains.output = cd_output = ClockDomain(reset_less=True)
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m.submodules.buf = buf = io.FFBuffer(io.Direction.Output, port, o_domain="output")
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m.d.comb += buf.o.eq(pin.o)
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m.d.comb += cd_output.clk.eq(pin.o_clk)
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elif pin.xdr == 2:
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m.domains.output = cd_output = ClockDomain(reset_less=True)
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m.submodules.buf = buf = io.DDRBuffer(io.Direction.Output, port, o_domain="output")
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m.d.comb += buf.o[0].eq(pin.o0)
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m.d.comb += buf.o[1].eq(pin.o1)
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m.d.comb += cd_output.clk.eq(pin.o_clk)
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if pin.dir == "oe":
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m.d.comb += buf.oe.eq(pin.oe)
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return m
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get_tristate = get_output
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def get_input_output(self, pin, port, attrs, invert):
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self._check_feature("single-ended input/output", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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if pin.xdr == 0:
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m.submodules.buf = buf = io.Buffer(io.Direction.Bidir, port)
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m.d.comb += pin.i.eq(buf.i)
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m.d.comb += buf.o.eq(pin.o)
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m.d.comb += buf.oe.eq(pin.oe)
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elif pin.xdr == 1:
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m.domains.input = cd_input = ClockDomain(reset_less=True)
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m.domains.output = cd_output = ClockDomain(reset_less=True)
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m.submodules.buf = buf = io.FFBuffer(io.Direction.Bidir, port, i_domain="input", o_domain="output")
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m.d.comb += pin.i.eq(buf.i)
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m.d.comb += buf.o.eq(pin.o)
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m.d.comb += buf.oe.eq(pin.oe)
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m.d.comb += cd_input.clk.eq(pin.i_clk)
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m.d.comb += cd_output.clk.eq(pin.o_clk)
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elif pin.xdr == 2:
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m.domains.input = cd_input = ClockDomain(reset_less=True)
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m.domains.output = cd_output = ClockDomain(reset_less=True)
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m.submodules.buf = buf = io.DDRBuffer(io.Direction.Bidir, port, i_domain="input", o_domain="output")
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m.d.comb += pin.i0.eq(buf.i[0])
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m.d.comb += pin.i1.eq(buf.i[1])
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m.d.comb += buf.o[0].eq(pin.o0)
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m.d.comb += buf.o[1].eq(pin.o1)
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m.d.comb += buf.oe.eq(pin.oe)
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m.d.comb += cd_input.clk.eq(pin.i_clk)
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m.d.comb += cd_output.clk.eq(pin.o_clk)
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return m
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get_diff_input = get_input
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get_diff_output = get_output
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get_diff_tristate = get_tristate
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get_diff_input_output = get_input_output
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class TemplatedPlatform(Platform):
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toolchain = property(abstractmethod(lambda: None))
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@ -1,8 +1,8 @@
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from collections import OrderedDict
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from ..hdl._ast import *
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from ..lib.io import *
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from ..lib import wiring
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from ..hdl import *
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from ..hdl._ast import SignalDict
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from ..lib import wiring, io
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from .dsl import *
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@ -24,6 +24,78 @@ class PortMetadata:
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self.attrs = attrs
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class PinBuffer(Elaboratable):
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def __init__(self, pin, port):
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if pin.xdr not in (0, 1, 2):
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raise ValueError(f"Unsupported 'xdr' value {pin.xdr}")
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self.pin = pin
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self.port = port
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def elaborate(self, platform):
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m = Module()
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if self.pin.dir == "i":
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if self.pin.xdr == 0:
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m.submodules.buf = buf = io.Buffer(io.Direction.Input, self.port)
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m.d.comb += self.pin.i.eq(buf.i)
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elif self.pin.xdr == 1:
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m.domains.input = cd_input = ClockDomain(reset_less=True)
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m.submodules.buf = buf = io.FFBuffer(io.Direction.Input, self.port, i_domain="input")
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m.d.comb += self.pin.i.eq(buf.i)
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m.d.comb += cd_input.clk.eq(self.pin.i_clk)
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elif self.pin.xdr == 2:
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m.domains.input = cd_input = ClockDomain(reset_less=True)
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m.submodules.buf = buf = io.DDRBuffer(io.Direction.Input, self.port, i_domain="input")
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m.d.comb += self.pin.i0.eq(buf.i[0])
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m.d.comb += self.pin.i1.eq(buf.i[1])
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m.d.comb += cd_input.clk.eq(self.pin.i_clk)
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if self.pin.dir in ("o", "oe"):
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if self.pin.xdr == 0:
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m.submodules.buf = buf = io.Buffer(io.Direction.Output, self.port)
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m.d.comb += buf.o.eq(self.pin.o)
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elif self.pin.xdr == 1:
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m.domains.output = cd_output = ClockDomain(reset_less=True)
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m.submodules.buf = buf = io.FFBuffer(io.Direction.Output, self.port, o_domain="output")
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m.d.comb += buf.o.eq(self.pin.o)
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m.d.comb += cd_output.clk.eq(self.pin.o_clk)
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elif self.pin.xdr == 2:
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m.domains.output = cd_output = ClockDomain(reset_less=True)
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m.submodules.buf = buf = io.DDRBuffer(io.Direction.Output, self.port, o_domain="output")
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m.d.comb += buf.o[0].eq(self.pin.o0)
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m.d.comb += buf.o[1].eq(self.pin.o1)
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m.d.comb += cd_output.clk.eq(self.pin.o_clk)
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if self.pin.dir == "oe":
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m.d.comb += buf.oe.eq(self.pin.oe)
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if self.pin.dir == "io":
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if self.pin.xdr == 0:
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m.submodules.buf = buf = io.Buffer(io.Direction.Bidir, self.port)
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m.d.comb += self.pin.i.eq(buf.i)
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m.d.comb += buf.o.eq(self.pin.o)
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m.d.comb += buf.oe.eq(self.pin.oe)
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elif self.pin.xdr == 1:
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m.domains.input = cd_input = ClockDomain(reset_less=True)
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m.domains.output = cd_output = ClockDomain(reset_less=True)
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m.submodules.buf = buf = io.FFBuffer(io.Direction.Bidir, self.port, i_domain="input", o_domain="output")
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m.d.comb += self.pin.i.eq(buf.i)
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m.d.comb += buf.o.eq(self.pin.o)
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m.d.comb += buf.oe.eq(self.pin.oe)
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m.d.comb += cd_input.clk.eq(self.pin.i_clk)
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m.d.comb += cd_output.clk.eq(self.pin.o_clk)
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elif self.pin.xdr == 2:
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m.domains.input = cd_input = ClockDomain(reset_less=True)
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m.domains.output = cd_output = ClockDomain(reset_less=True)
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m.submodules.buf = buf = io.DDRBuffer(io.Direction.Bidir, self.port, i_domain="input", o_domain="output")
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m.d.comb += self.pin.i0.eq(buf.i[0])
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m.d.comb += self.pin.i1.eq(buf.i[1])
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m.d.comb += buf.o[0].eq(self.pin.o0)
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m.d.comb += buf.o[1].eq(self.pin.o1)
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m.d.comb += buf.oe.eq(self.pin.oe)
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m.d.comb += cd_input.clk.eq(self.pin.i_clk)
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m.d.comb += cd_output.clk.eq(self.pin.o_clk)
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return m
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class ResourceManager:
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def __init__(self, resources, connectors):
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self.resources = OrderedDict()
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@ -33,8 +105,11 @@ class ResourceManager:
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self.connectors = OrderedDict()
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self._conn_pins = OrderedDict()
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# Constraint lists
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# List of all IOPort instances created
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self._ports = []
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# List of (pin, port, buffer) pairs for non-dir="-" requests.
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self._pins = []
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# Constraint list
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self._clocks = SignalDict()
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self.add_resources(resources)
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@ -139,11 +214,12 @@ class ResourceManager:
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direction = phys.dir
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if isinstance(phys, Pins):
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phys_names = phys.map_names(self._conn_pins, resource)
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io = IOPort(len(phys), name="__".join(path) + "__io", metadata=[
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iop = IOPort(len(phys), name="__".join(path) + "__io", metadata=[
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PortMetadata(name, attrs)
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for name in phys_names
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])
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port = SingleEndedPort(io, invert=phys.invert, direction=direction)
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self._ports.append(iop)
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port = io.SingleEndedPort(iop, invert=phys.invert, direction=direction)
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if isinstance(phys, DiffPairs):
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phys_names_p = phys.p.map_names(self._conn_pins, resource)
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phys_names_n = phys.n.map_names(self._conn_pins, resource)
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@ -156,11 +232,8 @@ class ResourceManager:
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PortMetadata(name, attrs)
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for name in phys_names_n
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])
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port = DifferentialPort(p, n, invert=phys.invert, direction=direction)
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if dir == "-":
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pin = None
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else:
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pin = wiring.flipped(Pin(len(phys), dir, xdr=xdr, path=path))
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self._ports += [p, n]
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port = io.DifferentialPort(p, n, invert=phys.invert, direction=direction)
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for phys_name in phys_names:
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if phys_name in self._phys_reqd:
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@ -171,12 +244,16 @@ class ResourceManager:
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".".join(self._phys_reqd[phys_name])))
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self._phys_reqd[phys_name] = path
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self._ports.append((resource, pin, port, attrs))
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if dir == "-":
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return port
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else:
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pin = wiring.flipped(io.Pin(len(phys), dir, xdr=xdr, path=path))
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buffer = PinBuffer(pin, port)
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self._pins.append((pin, port, buffer))
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if pin is not None and resource.clock is not None:
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self.add_clock_constraint(pin.i, resource.clock.frequency)
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return pin if pin is not None else port
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if resource.clock is not None:
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self.add_clock_constraint(pin.i, resource.clock.frequency)
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return pin
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else:
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assert False # :nocov:
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@ -188,56 +265,19 @@ class ResourceManager:
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self._requested[resource.name, resource.number] = value
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return value
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def iter_single_ended_pins(self):
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for res, pin, port, attrs in self._ports:
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if pin is None:
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continue
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if isinstance(res.ios[0], Pins):
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yield pin, port, attrs, res.ios[0].invert
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def iter_differential_pins(self):
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for res, pin, port, attrs in self._ports:
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if pin is None:
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continue
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if isinstance(res.ios[0], DiffPairs):
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yield pin, port, attrs, res.ios[0].invert
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def should_skip_port_component(self, port, attrs, component):
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return False
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def iter_pins(self):
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yield from self._pins
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def iter_ports(self):
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for res, pin, port, attrs in self._ports:
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if isinstance(res.ios[0], Pins):
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if not self.should_skip_port_component(port, attrs, "io"):
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yield port.io
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elif isinstance(res.ios[0], DiffPairs):
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if not self.should_skip_port_component(port, attrs, "p"):
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yield port.p
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if not self.should_skip_port_component(port, attrs, "n"):
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yield port.n
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else:
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assert False
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def iter_port_constraints(self):
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for res, pin, port, attrs in self._ports:
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if isinstance(res.ios[0], Pins):
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if not self.should_skip_port_component(port, attrs, "io"):
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yield port.io.name, res.ios[0].map_names(self._conn_pins, res), attrs
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elif isinstance(res.ios[0], DiffPairs):
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if not self.should_skip_port_component(port, attrs, "p"):
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yield port.p.name, res.ios[0].p.map_names(self._conn_pins, res), attrs
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if not self.should_skip_port_component(port, attrs, "n"):
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yield port.n.name, res.ios[0].n.map_names(self._conn_pins, res), attrs
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else:
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assert False
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yield from self._ports
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def iter_port_constraints_bits(self):
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for port_name, pin_names, attrs in self.iter_port_constraints():
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if len(pin_names) == 1:
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yield port_name, pin_names[0], attrs
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for port in self._ports:
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if len(port) == 1:
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yield port.name, port.metadata[0].name, port.metadata[0].attrs
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else:
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for bit, pin_name in enumerate(pin_names):
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yield f"{port_name}[{bit}]", pin_name, attrs
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for bit, meta in enumerate(port.metadata):
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yield f"{port.name}[{bit}]", meta.name, meta.attrs
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def add_clock_constraint(self, clock, frequency):
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if isinstance(clock, ClockSignal):
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@ -267,11 +307,11 @@ class ResourceManager:
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# Constraints on nets with no corresponding input pin (e.g. PLL or SERDES outputs) are not
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# affected.
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pin_i_to_port = SignalDict()
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for res, pin, port, attrs in self._ports:
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for pin, port, _fragment in self._pins:
|
||||
if hasattr(pin, "i"):
|
||||
if isinstance(res.ios[0], Pins):
|
||||
if isinstance(port, io.SingleEndedPort):
|
||||
pin_i_to_port[pin.i] = port.io
|
||||
elif isinstance(res.ios[0], DiffPairs):
|
||||
elif isinstance(port, io.DifferentialPort):
|
||||
pin_i_to_port[pin.i] = port.p
|
||||
else:
|
||||
assert False
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue