build.{plat,res}: post-lib.io cleanup.
This commit is contained in:
Wanda
Catherine
parent
7fe62f810b
commit
cf534489a2
3 changed files with 179 additions and 272 deletions
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@ -63,12 +63,15 @@ class ResourceManagerTestCase(FHDLTestCase):
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self.assertEqual(user_led.width, 1)
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self.assertEqual(user_led.dir, "o")
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ports = list(self.cm.iter_ports())
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self.assertEqual(len(ports), 1)
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pins = list(self.cm.iter_pins())
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(pin, port, buffer), = pins
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self.assertEqual(list(self.cm.iter_port_constraints()), [
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("user_led_0__io", ["A0"], {})
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])
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self.assertIs(pin, user_led)
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self.assertEqual(port.io.name, "user_led_0__io")
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self.assertEqual(port.io.metadata[0].name, "A0")
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self.assertEqual(port.io.metadata[0].attrs, {})
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self.assertEqual(port.direction, Direction.Output)
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self.assertEqual(port.invert, (False,))
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def test_request_with_dir(self):
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i2c = self.cm.request("i2c", 0, dir={"sda": "o"})
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@ -79,24 +82,13 @@ class ResourceManagerTestCase(FHDLTestCase):
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i2c = self.cm.request("i2c", 0)
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self.assertEqual(i2c.sda.dir, "io")
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ports = list(self.cm.iter_ports())
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self.assertEqual(len(ports), 2)
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scl, sda = ports
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self.assertEqual(ports[1].name, "i2c_0__sda__io")
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self.assertEqual(ports[1].width, 1)
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scl_info, sda_info = self.cm.iter_single_ended_pins()
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self.assertIs(scl_info[0], i2c.scl)
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self.assertIs(scl_info[1].io, scl)
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self.assertEqual(scl_info[2], {})
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self.assertEqual(scl_info[3], False)
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self.assertIs(sda_info[0], i2c.sda)
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self.assertIs(sda_info[1].io, sda)
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self.assertEqual(list(self.cm.iter_port_constraints()), [
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("i2c_0__scl__io", ["N10"], {}),
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("i2c_0__sda__io", ["N11"], {})
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])
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((scl_pin, scl_port, _), (sda_pin, sda_port, _)) = self.cm.iter_pins()
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self.assertIs(scl_pin, i2c.scl)
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self.assertIs(sda_pin, i2c.sda)
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self.assertEqual(scl_port.io.name, "i2c_0__scl__io")
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self.assertEqual(scl_port.io.metadata[0].name, "N10")
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self.assertEqual(sda_port.io.name, "i2c_0__sda__io")
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self.assertEqual(sda_port.io.metadata[0].name, "N11")
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def test_request_diffpairs(self):
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clk100 = self.cm.request("clk100", 0)
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@ -104,25 +96,14 @@ class ResourceManagerTestCase(FHDLTestCase):
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self.assertEqual(clk100.dir, "i")
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self.assertEqual(clk100.width, 1)
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ports = list(self.cm.iter_ports())
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self.assertEqual(len(ports), 2)
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p, n = ports
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self.assertEqual(p.name, "clk100_0__p")
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self.assertEqual(p.width, clk100.width)
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self.assertEqual(n.name, "clk100_0__n")
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self.assertEqual(n.width, clk100.width)
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clk100_info, = self.cm.iter_differential_pins()
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self.assertIs(clk100_info[0], clk100)
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self.assertIs(clk100_info[1].p, p)
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self.assertIs(clk100_info[1].n, n)
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self.assertEqual(clk100_info[2], {})
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self.assertEqual(clk100_info[3], False)
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self.assertEqual(list(self.cm.iter_port_constraints()), [
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("clk100_0__p", ["H1"], {}),
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("clk100_0__n", ["H2"], {}),
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])
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(clk100_pin, clk100_port, _), = self.cm.iter_pins()
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self.assertIs(clk100_pin, clk100)
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self.assertEqual(clk100_port.p.name, "clk100_0__p")
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self.assertEqual(clk100_port.p.width, clk100.width)
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self.assertEqual(clk100_port.n.name, "clk100_0__n")
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self.assertEqual(clk100_port.n.width, clk100.width)
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self.assertEqual(clk100_port.p.metadata[0].name, "H1")
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self.assertEqual(clk100_port.n.metadata[0].name, "H2")
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def test_request_inverted(self):
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new_resources = [
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@ -133,39 +114,27 @@ class ResourceManagerTestCase(FHDLTestCase):
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cs = self.cm.request("cs")
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clk = self.cm.request("clk")
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cs_io, clk_p, clk_n = self.cm.iter_ports()
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(
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(cs_pin, cs_port, _),
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(clk_pin, clk_port, _),
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) = self.cm.iter_pins()
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cs_info, = self.cm.iter_single_ended_pins()
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self.assertIs(cs_info[0], cs)
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self.assertIs(cs_info[1].io, cs_io)
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self.assertEqual(cs_info[2], {})
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self.assertEqual(cs_info[3], True)
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clk_info, = self.cm.iter_differential_pins()
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self.assertIs(clk_info[0], clk)
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self.assertIs(clk_info[1].p, clk_p)
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self.assertIs(clk_info[1].n, clk_n)
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self.assertEqual(clk_info[2], {})
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self.assertEqual(clk_info[3], True)
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self.assertIs(cs_pin, cs)
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self.assertEqual(cs_port.invert, (True,))
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self.assertIs(clk_pin, clk)
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self.assertEqual(clk_port.invert, (True,))
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def test_request_raw(self):
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clk50 = self.cm.request("clk50", 0, dir="-")
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self.assertIsInstance(clk50, SingleEndedPort)
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self.assertIsInstance(clk50.io, IOPort)
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ports = list(self.cm.iter_ports())
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self.assertEqual(len(ports), 1)
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self.assertIs(ports[0], clk50.io)
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def test_request_raw_diffpairs(self):
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clk100 = self.cm.request("clk100", 0, dir="-")
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self.assertIsInstance(clk100, DifferentialPort)
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self.assertIsInstance(clk100.p, IOPort)
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self.assertIsInstance(clk100.n, IOPort)
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ports = list(self.cm.iter_ports())
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self.assertEqual(len(ports), 2)
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self.assertIs(ports[0], clk100.p)
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self.assertIs(ports[1], clk100.n)
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def test_request_via_connector(self):
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self.cm.add_resources([
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Resource("spi", 0,
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@ -176,12 +145,20 @@ class ResourceManagerTestCase(FHDLTestCase):
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)
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])
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spi0 = self.cm.request("spi", 0)
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self.assertEqual(list(self.cm.iter_port_constraints()), [
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("spi_0__ss__io", ["B0"], {}),
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("spi_0__clk__io", ["B1"], {}),
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("spi_0__miso__io", ["B2"], {}),
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("spi_0__mosi__io", ["B3"], {}),
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])
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(
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(ss_pin, ss_port, _),
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(clk_pin, clk_port, _),
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(miso_pin, miso_port, _),
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(mosi_pin, mosi_port, _),
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) = self.cm.iter_pins()
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self.assertIs(ss_pin, spi0.ss)
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self.assertIs(clk_pin, spi0.clk)
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self.assertIs(miso_pin, spi0.miso)
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self.assertIs(mosi_pin, spi0.mosi)
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self.assertEqual(ss_port.io.metadata[0].name, "B0")
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self.assertEqual(clk_port.io.metadata[0].name, "B1")
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self.assertEqual(miso_port.io.metadata[0].name, "B2")
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self.assertEqual(mosi_port.io.metadata[0].name, "B3")
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def test_request_via_nested_connector(self):
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new_connectors = [
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@ -197,20 +174,31 @@ class ResourceManagerTestCase(FHDLTestCase):
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)
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])
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spi0 = self.cm.request("spi", 0)
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self.assertEqual(list(self.cm.iter_port_constraints()), [
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("spi_0__ss__io", ["B0"], {}),
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("spi_0__clk__io", ["B1"], {}),
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("spi_0__miso__io", ["B2"], {}),
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("spi_0__mosi__io", ["B3"], {}),
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])
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(
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(ss_pin, ss_port, _),
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(clk_pin, clk_port, _),
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(miso_pin, miso_port, _),
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(mosi_pin, mosi_port, _),
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) = self.cm.iter_pins()
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self.assertIs(ss_pin, spi0.ss)
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self.assertIs(clk_pin, spi0.clk)
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self.assertIs(miso_pin, spi0.miso)
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self.assertIs(mosi_pin, spi0.mosi)
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self.assertEqual(ss_port.io.metadata[0].name, "B0")
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self.assertEqual(clk_port.io.metadata[0].name, "B1")
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self.assertEqual(miso_port.io.metadata[0].name, "B2")
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self.assertEqual(mosi_port.io.metadata[0].name, "B3")
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def test_request_clock(self):
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clk100 = self.cm.request("clk100", 0)
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clk50 = self.cm.request("clk50", 0, dir="i")
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clk100_port_p, clk100_port_n, clk50_port = self.cm.iter_ports()
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(
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(clk100_pin, clk100_port, _),
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(clk50_pin, clk50_port, _),
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) = self.cm.iter_pins()
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self.assertEqual(list(self.cm.iter_clock_constraints()), [
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(clk100.i, clk100_port_p, 100e6),
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(clk50.i, clk50_port, 50e6)
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(clk100.i, clk100_port.p, 100e6),
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(clk50.i, clk50_port.io, 50e6)
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])
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def test_add_clock(self):
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