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back.rtlil: fix guard for division by zero.

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Oops... that should be checking the divisor, not the dividend. This
was discovered by running the test suite on cxxsim.
This commit is contained in:
whitequark 2020-07-15 04:09:58 +00:00
parent d714d78de1
commit d06add0aab
1 changed files with 1 additions and 1 deletions
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2
nmigen/back/rtlil.py
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@ -558,7 +558,7 @@ class _RHSValueCompiler(_ValueCompiler):
self.s.rtlil.cell("$mux", ports={ self.s.rtlil.cell("$mux", ports={
"\\A": divmod_res, "\\A": divmod_res,
"\\B": self(ast.Const(0, ast.Shape(res_bits, res_sign))), "\\B": self(ast.Const(0, ast.Shape(res_bits, res_sign))),
"\\S": self(lhs == 0), "\\S": self(rhs == 0),
"\\Y": res, "\\Y": res,
}, params={ }, params={
"WIDTH": res_bits "WIDTH": res_bits