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tests.hdl.dsl: add tests for mis-nested Switch/Case and FSM/State statements

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Thomas Watson 2021-05-10 21:02:29 -05:00 committed by whitequark
parent 7443f89200
commit d09dedfb48
1 changed files with 26 additions and 0 deletions
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26
tests/test_hdl_dsl.py
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@ -504,6 +504,15 @@ class DSLTestCase(FHDLTestCase):
with m.If(self.s2):
pass
def test_Case_wrong_nested(self):
m = Module()
with m.Switch(self.s1):
with m.Case(0):
with self.assertRaisesRegex(SyntaxError,
r"^Case is not permitted outside of Switch$"):
with m.Case(1):
pass
def test_FSM_basic(self):
a = Signal()
b = Signal()
@ -660,6 +669,23 @@ class DSLTestCase(FHDLTestCase):
with m.If(self.s2):
pass
def test_State_outside_FSM_wrong(self):
m = Module()
with self.assertRaisesRegex(SyntaxError,
r"^FSM State is not permitted outside of FSM"):
with m.State("FOO"):
pass
def test_FSM_State_wrong_nested(self):
m = Module()
with m.FSM():
with m.State("FOO"):
with self.assertRaisesRegex(SyntaxError,
r"^FSM State is not permitted outside of FSM"):
with m.State("BAR"):
pass
def test_auto_pop_ctrl(self):
m = Module()
with m.If(self.w1):