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back.rtlil: actually match shape of left hand side.

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This comes up in code such as:
  Array([Signal(1), Signal(8)]).eq(Const(0, 8))
This commit is contained in:
whitequark 2019-08-03 23:43:57 +00:00
parent 999a2f612a
commit d0ac8bf789
1 changed files with 9 additions and 2 deletions
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11
nmigen/back/rtlil.py
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@ -572,8 +572,15 @@ class _LHSValueCompiler(_ValueCompiler):
raise TypeError # :nocov: raise TypeError # :nocov:
def match_shape(self, value, new_bits, new_sign): def match_shape(self, value, new_bits, new_sign):
assert value.shape() == (new_bits, new_sign) value_bits, value_sign = value.shape()
return self(value) if new_bits == value_bits:
return self(value)
elif new_bits < value_bits:
return self(ast.Slice(value, 0, new_bits))
else: # new_bits > value_bits
# It is legal to assign to constants on LHS in RTLIL; such assignments are ignored.
dummy_bits = new_bits - value_bits
return "{{ {}'{} {} }}".format(dummy_bits, "x" * dummy_bits, self(value))
def on_Signal(self, value): def on_Signal(self, value):
if value not in self.s.driven: if value not in self.s.driven: