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lib.fifo: use proper clock domains in AsyncFIFO tests

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Robin Ole Heinemann 2021-01-03 00:13:46 +01:00 committed by whitequark
parent 76efe862fa
commit d15705cf4f
1 changed files with 4 additions and 4 deletions
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8
tests/test_lib_fifo.py
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@ -312,16 +312,16 @@ class AsyncFIFOSimCase(FHDLTestCase):
for i in range(fill_in): for i in range(fill_in):
yield fifo.w_data.eq(i) yield fifo.w_data.eq(i)
yield fifo.w_en.eq(1) yield fifo.w_en.eq(1)
yield yield Tick("write")
yield fifo.w_en.eq(0) yield fifo.w_en.eq(0)
yield yield Tick("write")
yield yield Tick("write")
self.assertEqual((yield fifo.w_level), expected_level) self.assertEqual((yield fifo.w_level), expected_level)
yield write_done.eq(1) yield write_done.eq(1)
def read_process(): def read_process():
while not (yield write_done): while not (yield write_done):
yield yield Tick("read")
self.assertEqual((yield fifo.r_level), expected_level) self.assertEqual((yield fifo.r_level), expected_level)
simulator = Simulator(fifo) simulator = Simulator(fifo)