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back.verilog, back.rtlil: map path elements to str

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meta 2024-04-18 18:06:55 -05:00 committed by Catherine
parent dde8334031
commit d2b2c9b06a
2 changed files with 2 additions and 2 deletions
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2
amaranth/back/rtlil.py
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@ -1289,7 +1289,7 @@ def convert(elaboratable, name="top", platform=None, *, ports=None, emit_src=Tru
dir = _ir.PortDirection.Input
else:
dir = _ir.PortDirection.Output
ports["__".join(path)] = (value, dir)
ports["__".join(map(str, path))] = (value, dir)
elif ports is None:
raise TypeError("The `convert()` function requires a `ports=` argument")
fragment = _ir.Fragment.get(elaboratable, platform)

2
amaranth/back/verilog.py
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@ -54,7 +54,7 @@ def convert(elaboratable, name="top", platform=None, *, ports=None, emit_src=Tru
dir = _ir.PortDirection.Input
else:
dir = _ir.PortDirection.Output
ports["__".join(path)] = (value, dir)
ports["__".join(map(str, path))] = (value, dir)
elif ports is None:
raise TypeError("The `convert()` function requires a `ports=` argument")
fragment = _ir.Fragment.get(elaboratable, platform)