fhdl.cd: rename ClockDomain.{reset→rst}.

nmigen/back/rtlil.py

@@ -415,7 +415,7 @@ def convert_fragment(builder, fragment, name, top, clock_domains):
         for cd_name, _ in fragment.iter_sync():
             cd = clock_domains[cd_name]
             xformer(cd.clk)
-            xformer(cd.reset)
+            xformer(cd.rst)
 
         # Transform all subfragments to their respective cells. Transforming signals connected
         # to their ports into wires eagerly makes sure they get sensible (prefixed with submodule
@@ -488,7 +488,7 @@ def convert_fragment(builder, fragment, name, top, clock_domains):
                     cd = clock_domains[cd_name]
                     triggers.append(("posedge", xformer(cd.clk)))
                     if cd.async_reset:
-                        triggers.append(("posedge", xformer(cd.reset)))
+                        triggers.append(("posedge", xformer(cd.rst)))
                 else:
                     raise ValueError("Clock domain {} not found in design".format(cd_name))
 
@@ -513,7 +513,7 @@ def convert(fragment, ports=[], clock_domains={}):
     # Clock domain reset always takes priority over all other logic. To ensure this, insert
     # decision trees for clock domain reset as the very last step before synthesis.
     fragment = xfrm.ResetInserter({
-        cd.name: cd.reset for cd in clock_domains.values() if cd.reset is not None
+        cd.name: cd.rst for cd in clock_domains.values() if cd.rst is not None
     })(fragment)
 
     ins, outs = fragment._propagate_ports(ports, clock_domains)

nmigen/fhdl/cd.py

@@ -27,7 +27,7 @@ class ClockDomain:
     clk : Signal, inout
         The clock for this domain. Can be driven or used to drive other signals (preferably
         in combinatorial context).
-    reset : Signal or None, inout
+    rst : Signal or None, inout
         Reset signal for this domain. Can be driven or used to drive.
     """
     def __init__(self, name=None, reset_less=False, async_reset=False):
@@ -41,8 +41,8 @@ class ClockDomain:
 
         self.clk = Signal(name=self.name + "_clk")
         if reset_less:
-            self.reset = None
+            self.rst = None
         else:
-            self.reset = Signal(name=self.name + "_reset")
+            self.rst = Signal(name=self.name + "_rst")
 
         self.async_reset = async_reset

nmigen/fhdl/ir.py

@@ -58,8 +58,8 @@ class Fragment:
         for cd_name, _ in self.iter_sync():
             cd = clock_domains[cd_name]
             self_used.add(cd.clk)
-            if cd.reset is not None:
+            if cd.rst is not None:
-                self_used.add(cd.reset)
+                self_used.add(cd.rst)
 
         # Our input ports are all the signals we're using but not driving. This is an over-
         # approximation: some of these signals may be driven by our subfragments.