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back.rtlil: use one $meminit cell, not one per word.

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This is *far* more efficient.
This commit is contained in:
whitequark 2018-12-24 09:30:47 +00:00
parent 98f554aa08
commit d47c1f8a8a
1 changed files with 12 additions and 10 deletions
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8
nmigen/back/rtlil.py
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@ -644,19 +644,21 @@ def convert_fragment(builder, fragment, name, top):
memories[memory] = module.memory(width=memory.width, size=memory.depth, memories[memory] = module.memory(width=memory.width, size=memory.depth,
name=memory.name) name=memory.name)
addr_bits = bits_for(memory.depth) addr_bits = bits_for(memory.depth)
data_parts = ["{}'".format(memory.width * memory.depth)]
for addr in range(memory.depth): for addr in range(memory.depth):
if addr < len(memory.init): if addr < len(memory.init):
data = memory.init[addr] data = memory.init[addr]
else: else:
data = 0 data = 0
data_parts.append("{:0{}b}".format(data, memory.width))
module.cell("$meminit", ports={ module.cell("$meminit", ports={
"\\ADDR": rhs_compiler(ast.Const(addr, addr_bits)), "\\ADDR": rhs_compiler(ast.Const(0, addr_bits)),
"\\DATA": rhs_compiler(ast.Const(data, memory.width)), "\\DATA": "".join(data_parts),
}, params={ }, params={
"MEMID": memories[memory], "MEMID": memories[memory],
"ABITS": addr_bits, "ABITS": addr_bits,
"WIDTH": memory.width, "WIDTH": memory.width,
"WORDS": 1, "WORDS": memory.depth,
"PRIORITY": 0, "PRIORITY": 0,
}) })