vendor.xilinx_spartan6: implement.
This commit is contained in:
Jean-François Nguyen
whitequark
parent
2b3a0e9fa0
commit
d5ba26b174
267
nmigen/vendor/xilinx_spartan6.py
vendored
Normal file
267
nmigen/vendor/xilinx_spartan6.py
vendored
Normal file
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from abc import abstractproperty
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from ..hdl.ast import *
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from ..hdl.dsl import *
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from ..hdl.ir import *
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from ..build import *
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__all__ = ["XilinxSpartan6Platform"]
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class XilinxSpartan6Platform(TemplatedPlatform):
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"""
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Required tools:
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* ISE toolchain:
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* ``xst``
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* ``ngdbuild``
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* ``map``
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* ``par``
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* ``bitgen``
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Available overrides:
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* ``script_after_run``: inserts commands after ``run`` in XST script.
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* ``add_constraints``: inserts commands in UCF file.
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* ``xst_opts``: adds extra options for XST.
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* ``ngdbuild_opts``: adds extra options for NGDBuild.
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* ``map_opts``: adds extra options for MAP.
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* ``par_opts``: adds extra options for PAR.
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* ``bitgen_opts``: adds extra options for BitGen.
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Build products:
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* ``{{name}}.srp``: synthesis report.
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* ``{{name}}.ngc``: synthesized RTL.
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* ``{{name}}.bld``: NGDBuild log.
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* ``{{name}}.ngd``: design database.
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* ``{{name}}_map.map``: MAP log.
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* ``{{name}}_map.mrp``: mapping report.
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* ``{{name}}_map.ncd``: mapped netlist.
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* ``{{name}}.pcf``: physical constraints.
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* ``{{name}}_par.par``: PAR log.
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* ``{{name}}_par_pad.txt``: I/O usage report.
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* ``{{name}}_par.ncd``: place and routed netlist.
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* ``{{name}}.drc``: DRC report.
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* ``{{name}}.bgn``: BitGen log.
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* ``{{name}}.bit``: binary bitstream.
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"""
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device = abstractproperty()
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package = abstractproperty()
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speedgrade = abstractproperty()
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file_templates = {
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**TemplatedPlatform.build_script_templates,
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"{{name}}.v": r"""
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/* {{autogenerated}} */
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{{emit_design("verilog")}}
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""",
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"{{name}}.prj": r"""
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# {{autogenerated}}
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{% for file in platform.extra_files -%}
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{% if file.endswith(".v") %}
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verilog work {{file}}
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{% endif %}
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{% endfor %}
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verilog work {{name}}.v
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""",
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"{{name}}.xst": r"""
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# {{autogenerated}}
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run
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-ifn {{name}}.prj
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-ofn {{name}}.ngc
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-top {{name}}
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-p {{platform.device}}{{platform.package}}-{{platform.speedgrade}}
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{{get_override("script_after_run")|default("# (script_after_run placeholder)")}}
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""",
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"{{name}}.ucf": r"""
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# {{autogenerated}}
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{% for port_name, pin_name, attrs in platform.iter_port_constraints_bits() -%}
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{% set port_name = port_name|replace("[", "<")|replace("]", ">") -%}
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NET "{{port_name}}" LOC={{pin_name}};
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{% for attr_name, attr_value in attrs.items() -%}
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NET "{{port_name}}" {{attr_name}}={{attr_value}};
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{% endfor %}
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{% endfor %}
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{% for signal, frequency in platform.iter_clock_constraints() -%}
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NET "{{signal.name}}" TNM_NET="PRD{{signal.name}}";
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TIMESPEC "TS{{signal.name}}"=PERIOD "PRD{{signal.name}}" {{1000000000/frequency}} ns HIGH 50%;
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{% endfor %}
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{{get_override("add_constraints")|default("# (add_constraints placeholder)")}}
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"""
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}
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command_templates = [
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r"""
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{{get_tool("xst")}}
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{{get_override("xst_opts")|join(" ")}}
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-ifn {{name}}.xst
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""",
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r"""
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{{get_tool("ngdbuild")}}
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{{quiet("-quiet")}}
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{{verbose("-verbose")}}
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{{get_override("ngdbuild_opts")|join(" ")}}
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-uc {{name}}.ucf
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{{name}}.ngc
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""",
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r"""
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{{get_tool("map")}}
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{{verbose("-detail")}}
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{{get_override("map_opts")|default(["-w"])|join(" ")}}
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-o {{name}}_map.ncd
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{{name}}.ngd
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{{name}}.pcf
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""",
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r"""
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{{get_tool("par")}}
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{{get_override("par_opts")|default(["-w"])|join(" ")}}
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{{name}}_map.ncd
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{{name}}_par.ncd
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{{name}}.pcf
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""",
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r"""
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{{get_tool("bitgen")}}
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{{get_override("bitgen_opts")|default(["-w"])|join(" ")}}
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{{name}}_par.ncd
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{{name}}.bit
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"""
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]
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def _get_dff(self, m, clk, d, q):
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# SDR I/O is performed by packing a flip-flop into the pad IOB.
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for bit in range(len(q)):
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_q = Signal()
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_q.attrs["IOB"] = "TRUE"
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m.submodules += Instance("FDCE",
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i_C=clk,
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i_CE=Const(1),
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i_CLR=Const(0),
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i_D=d[bit],
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o_Q=_q,
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)
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m.d.comb += q[bit].eq(_q)
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def get_input(self, pin, port, attrs):
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self._check_feature("single-ended input", pin, attrs,
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valid_xdrs=(0, 1), valid_attrs=True)
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m = Module()
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if pin.xdr == 1:
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self._get_dff(m, pin.i_clk, port, pin.i)
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else:
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m.d.comb += pin.i.eq(port)
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return m
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def get_output(self, pin, port, attrs):
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self._check_feature("single-ended output", pin, attrs,
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valid_xdrs=(0, 1), valid_attrs=True)
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m = Module()
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if pin.xdr == 1:
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self._get_dff(m, pin.o_clk, pin.o, port)
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else:
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m.d.comb += port.eq(pin.o)
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return m
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def get_tristate(self, pin, port, attrs):
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self._check_feature("single-ended tristate", pin, attrs,
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valid_xdrs=(0, 1), valid_attrs=True)
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m = Module()
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if pin.xdr == 1:
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o_ff = Signal.like(pin.o, name="{}_ff".format(pin.o.name))
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oe_ff = Signal.like(pin.oe, name="{}_ff".format(pin.oe.name))
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self._get_dff(m, pin.o_clk, pin.o, o_ff)
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self._get_dff(m, pin.o_clk, pin.oe, oe_ff)
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for bit in range(len(port)):
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m.submodules += Instance("OBUFT",
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i_T=~(oe_ff if pin.xdr == 1 else pin.oe),
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i_I=o_ff[bit] if pin.xdr == 1 else pin.o[bit],
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o_O=port[bit]
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)
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return m
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def get_input_output(self, pin, port, attrs):
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self._check_feature("single-ended input/output", pin, attrs,
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valid_xdrs=(0, 1), valid_attrs=True)
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m = Module()
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if pin.xdr == 1:
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o_ff = Signal.like(pin.o, name="{}_ff".format(pin.o.name))
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oe_ff = Signal.like(pin.oe, name="{}_ff".format(pin.oe.name))
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i_ff = Signal.like(pin.i, name="{}_ff".format(pin.i.name))
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self._get_dff(m, pin.o_clk, pin.o, o_ff)
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self._get_dff(m, pin.o_clk, pin.oe, oe_ff)
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self._get_dff(m, pin.i_clk, i_ff, pin.i)
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for bit in range(len(port)):
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m.submodules += Instance("IOBUF",
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i_T=~(oe_ff if pin.xdr == 1 else pin.oe),
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i_I=o_ff[bit] if pin.xdr == 1 else pin.o[bit],
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o_O=i_ff[bit] if pin.xdr == 1 else pin.i[bit],
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io_IO=port[bit]
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)
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return m
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def get_diff_input(self, pin, p_port, n_port, attrs):
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self._check_feature("differential input", pin, attrs,
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valid_xdrs=(0, 1), valid_attrs=True)
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m = Module()
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if pin.xdr == 1:
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i_ff = Signal.like(pin.i, name="{}_ff".format(pin.i.name))
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self._get_dff(m, pin.i_clk, i_ff, pin.i)
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for bit in range(len(p_port)):
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m.submodules += Instance("IBUFDS",
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i_I=p_port[bit],
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i_IB=n_port[bit],
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o_O=i_ff[bit] if pin.xdr == 1 else pin.i[bit]
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)
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return m
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def get_diff_output(self, pin, p_port, n_port, attrs):
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self._check_feature("differential output", pin, attrs,
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valid_xdrs=(0, 1), valid_attrs=True)
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m = Module()
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if pin.xdr == 1:
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o_ff = Signal.like(pin.o, name="{}_ff".format(pin.o.name))
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self._get_dff(m, pin.o_clk, pin.o, o_ff)
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for bit in range(len(p_port)):
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m.submodules += Instance("OBUFDS",
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o_O=p_port[bit],
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o_OB=n_port[bit],
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i_I=o_ff[bit] if pin.xdr == 1 else pin.o[bit]
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)
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return m
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def get_diff_tristate(self, pin, p_port, n_port, attrs):
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self._check_feature("differential tristate", pin, attrs,
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valid_xdrs=(0, 1), valid_attrs=True)
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m = Module()
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if pin.xdr == 1:
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o_ff = Signal.like(pin.o, name="{}_ff".format(pin.o.name))
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oe_ff = Signal.like(pin.oe, name="{}_ff".format(pin.oe.name))
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self._get_dff(m, pin.o_clk, pin.o, o_ff)
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self._get_dff(m, pin.o_clk, pin.oe, oe_ff)
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for bit in range(len(p_port)):
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m.submodules += Instance("OBUFTDS",
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i_T=~(oe_ff if pin.xdr == 1 else pin.oe),
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i_I=o_ff[bit] if pin.xdr == 1 else pin.o[bit],
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o_O=p_port[bit],
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o_OB=n_port[bit]
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)
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return m
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def get_diff_input_output(self, pin, p_port, n_port, attrs):
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self._check_feature("differential input/output", pin, attrs,
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valid_xdrs=(0, 1), valid_attrs=True)
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m = Module()
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if pin.xdr == 1:
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o_ff = Signal.like(pin.o, name="{}_ff".format(pin.o.name))
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oe_ff = Signal.like(pin.oe, name="{}_ff".format(pin.oe.name))
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i_ff = Signal.like(pin.i, name="{}_ff".format(pin.i.name))
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self._get_dff(m, pin.o_clk, pin.o, o_ff)
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self._get_dff(m, pin.o_clk, pin.oe, oe_ff)
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self._get_dff(m, pin.i_clk, i_ff, pin.i)
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for bit in range(len(p_port)):
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m.submodules += Instance("IOBUFDS",
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i_T=~(oe_ff if pin.xdr == 1 else pin.oe),
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i_I=o_ff[bit] if pin.xdr == 1 else pin.o[bit],
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o_O=i_ff[bit] if pin.xdr == 1 else pin.i[bit],
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io_IO=p_port[bit],
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io_IOB=n_port[bit]
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)
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return m
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