build.plat: TemplatedPlatform.iter_extra_files→Platform.iter_files.

This function was added in commit 20553b14 in the wrong place, with
the wrong name, and without tests. Fix all that.

nmigen/build/plat.py

@@ -63,6 +63,11 @@ class Platform(ResourceManager, metaclass=ABCMeta):
         else:
             self.extra_files[filename] = content
 
+    def iter_files(self, *suffixes):
+        for filename in self.extra_files:
+            if filename.endswith(suffixes):
+                yield filename
+
     @property
     def _toolchain_env_var(self):
         return f"NMIGEN_ENV_{self.toolchain}"
@@ -437,6 +442,3 @@ class TemplatedPlatform(Platform):
         for filename, content in self.extra_files.items():
             plan.add_file(filename, content)
         return plan
-
-    def iter_extra_files(self, *endswith):
-        return (f for f in self.extra_files if f.endswith(endswith))

nmigen/vendor/intel.py

@@ -82,13 +82,13 @@ class IntelPlatform(TemplatedPlatform):
                 set_global_assignment -name NUM_PARALLEL_PROCESSORS {{get_override("nproc")}}
             {% endif %}
 
-            {% for file in platform.iter_extra_files(".v") -%}
+            {% for file in platform.iter_files(".v") -%}
                 set_global_assignment -name VERILOG_FILE {{file|tcl_quote}}
             {% endfor %}
-            {% for file in platform.iter_extra_files(".sv") -%}
+            {% for file in platform.iter_files(".sv") -%}
                 set_global_assignment -name SYSTEMVERILOG_FILE {{file|tcl_quote}}
             {% endfor %}
-            {% for file in platform.iter_extra_files(".vhd", ".vhdl") -%}
+            {% for file in platform.iter_files(".vhd", ".vhdl") -%}
                 set_global_assignment -name VHDL_FILE {{file|tcl_quote}}
             {% endfor %}
             set_global_assignment -name VERILOG_FILE {{name}}.v

nmigen/vendor/lattice_ecp5.py

@@ -112,13 +112,13 @@ class LatticeECP5Platform(TemplatedPlatform):
         """,
         "{{name}}.ys": r"""
             # {{autogenerated}}
-            {% for file in platform.iter_extra_files(".v") -%}
+            {% for file in platform.iter_files(".v") -%}
                 read_verilog {{get_override("read_verilog_opts")|options}} {{file}}
             {% endfor %}
-            {% for file in platform.iter_extra_files(".sv") -%}
+            {% for file in platform.iter_files(".sv") -%}
                 read_verilog -sv {{get_override("read_verilog_opts")|options}} {{file}}
             {% endfor %}
-            {% for file in platform.iter_extra_files(".il") -%}
+            {% for file in platform.iter_files(".il") -%}
                 read_ilang {{file}}
             {% endfor %}
             read_ilang {{name}}.il
@@ -210,7 +210,7 @@ class LatticeECP5Platform(TemplatedPlatform):
                 -dev {{platform.device}}-{{platform.speed}}{{platform.package}}{{platform.grade}} \
                 -lpf {{name}}.lpf \
                 -synthesis synplify
-            {% for file in platform.iter_extra_files(".v", ".sv", ".vhd", ".vhdl") -%}
+            {% for file in platform.iter_files(".v", ".sv", ".vhd", ".vhdl") -%}
                 prj_src add {{file|tcl_escape}}
             {% endfor %}
             prj_src add {{name}}.v

nmigen/vendor/lattice_ice40.py

@@ -114,13 +114,13 @@ class LatticeICE40Platform(TemplatedPlatform):
         """,
         "{{name}}.ys": r"""
             # {{autogenerated}}
-            {% for file in platform.iter_extra_files(".v") -%}
+            {% for file in platform.iter_files(".v") -%}
                 read_verilog {{get_override("read_verilog_opts")|options}} {{file}}
             {% endfor %}
-            {% for file in platform.iter_extra_files(".sv") -%}
+            {% for file in platform.iter_files(".sv") -%}
                 read_verilog -sv {{get_override("read_verilog_opts")|options}} {{file}}
             {% endfor %}
-            {% for file in platform.iter_extra_files(".il") -%}
+            {% for file in platform.iter_files(".il") -%}
                 read_ilang {{file}}
             {% endfor %}
             read_ilang {{name}}.il
@@ -212,7 +212,7 @@ class LatticeICE40Platform(TemplatedPlatform):
             -d {{platform.device}}
             -t {{platform.package}}
             {{get_override("lse_opts")|options|default("# (lse_opts placeholder)")}}
-            {% for file in platform.iter_extra_files(".v") -%}
+            {% for file in platform.iter_files(".v") -%}
                 -ver {{file}}
             {% endfor %}
             -ver {{name}}.v
@@ -223,7 +223,7 @@ class LatticeICE40Platform(TemplatedPlatform):
         """,
         "{{name}}_syn.prj": r"""
             # {{autogenerated}}
-            {% for file in platform.iter_extra_files(".v", ".sv", ".vhd", ".vhdl") -%}
+            {% for file in platform.iter_files(".v", ".sv", ".vhd", ".vhdl") -%}
                 add_file -verilog {{file|tcl_escape}}
             {% endfor %}
             add_file -verilog {{name}}.v

nmigen/vendor/lattice_machxo_2_3l.py

@@ -74,7 +74,7 @@ class LatticeMachXO2Or3LPlatform(TemplatedPlatform):
                 -dev {{platform.device}}-{{platform.speed}}{{platform.package}}{{platform.grade}} \
                 -lpf {{name}}.lpf \
                 -synthesis synplify
-            {% for file in platform.iter_extra_files(".v", ".sv", ".vhd", ".vhdl") -%}
+            {% for file in platform.iter_files(".v", ".sv", ".vhd", ".vhdl") -%}
                 prj_src add {{file|tcl_escape}}
             {% endfor %}
             prj_src add {{name}}.v

nmigen/vendor/quicklogic.py

@@ -82,7 +82,7 @@ class QuicklogicPlatform(TemplatedPlatform):
         r"""
         {{invoke_tool("symbiflow_synth")}}
             -t {{name}}
-            -v {% for file in platform.iter_extra_files(".v", ".sv", ".vhd", ".vhdl") -%} {{file}} {% endfor %} {{name}}.v
+            -v {% for file in platform.iter_files(".v", ".sv", ".vhd", ".vhdl") -%} {{file}} {% endfor %} {{name}}.v
             -d {{platform.device}}
             -p {{name}}.pcf
             -P {{platform.package}}

nmigen/vendor/xilinx_7series.py

@@ -99,12 +99,12 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
         "{{name}}.tcl": r"""
             # {{autogenerated}}
             create_project -force -name {{name}} -part {{platform._part}}
-            {% for file in platform.iter_extra_files(".v", ".sv", ".vhd", ".vhdl") -%}
+            {% for file in platform.iter_files(".v", ".sv", ".vhd", ".vhdl") -%}
                 add_files {{file|tcl_escape}}
             {% endfor %}
             add_files {{name}}.v
             read_xdc {{name}}.xdc
-            {% for file in platform.iter_extra_files(".xdc") -%}
+            {% for file in platform.iter_files(".xdc") -%}
                 read_xdc {{file|tcl_escape}}
             {% endfor %}
             {{get_override("script_after_read")|default("# (script_after_read placeholder)")}}
@@ -229,7 +229,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
         r"""
         {{invoke_tool("synth")}}
             -t {{name}}
-            -v {% for file in platform.iter_extra_files(".v", ".sv", ".vhd", ".vhdl") -%} {{file}} {% endfor %} {{name}}.v
+            -v {% for file in platform.iter_files(".v", ".sv", ".vhd", ".vhdl") -%} {{file}} {% endfor %} {{name}}.v
             -p {{platform._symbiflow_part_map.get(platform._part, platform._part)}}
             -x {{name}}.xdc
         """,

nmigen/vendor/xilinx_spartan_3_6.py

@@ -102,10 +102,10 @@ class XilinxSpartan3Or6Platform(TemplatedPlatform):
         """,
         "{{name}}.prj": r"""
             # {{autogenerated}}
-            {% for file in platform.iter_extra_files(".vhd", ".vhdl") -%}
+            {% for file in platform.iter_files(".vhd", ".vhdl") -%}
                 vhdl work {{file}}
             {% endfor %}
-            {% for file in platform.iter_extra_files(".v") -%}
+            {% for file in platform.iter_files(".v") -%}
                 verilog work {{file}}
             {% endfor %}
             verilog work {{name}}.v

nmigen/vendor/xilinx_ultrascale.py

@@ -73,12 +73,12 @@ class XilinxUltraScalePlatform(TemplatedPlatform):
         "{{name}}.tcl": r"""
             # {{autogenerated}}
             create_project -force -name {{name}} -part {{platform.device}}-{{platform.package}}-{{platform.speed}}
-            {% for file in platform.iter_extra_files(".v", ".sv", ".vhd", ".vhdl") -%}
+            {% for file in platform.iter_files(".v", ".sv", ".vhd", ".vhdl") -%}
                 add_files {{file|tcl_escape}}
             {% endfor %}
             add_files {{name}}.v
             read_xdc {{name}}.xdc
-            {% for file in platform.iter_extra_files(".xdc") -%}
+            {% for file in platform.iter_files(".xdc") -%}
                 read_xdc {{file|tcl_escape}}
             {% endfor %}
             {{get_override("script_after_read")|default("# (script_after_read placeholder)")}}

tests/test_build_plat.py

@@ -51,3 +51,14 @@ class PlatformTestCase(FHDLTestCase):
         with self.assertRaisesRegex(ValueError,
                 r"^File 'foo' already exists$"):
             self.platform.add_file("foo", "bar")
+
+    def test_iter_files(self):
+        self.platform.add_file("foo.v", "")
+        self.platform.add_file("bar.v", "")
+        self.platform.add_file("baz.vhd", "")
+        self.assertEqual(list(self.platform.iter_files(".v")),
+                         ["foo.v", "bar.v"])
+        self.assertEqual(list(self.platform.iter_files(".vhd")),
+                         ["baz.vhd"])
+        self.assertEqual(list(self.platform.iter_files(".v", ".vhd")),
+                         ["foo.v", "bar.v", "baz.vhd"])