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lib.fifo.AsyncFIFO: fix incorrect latency of r_level.

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Co-authored-by: Andrew Wygle <awygle@gmail.com>
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anuejn 2020-10-24 16:58:23 +02:00 • committed by GitHub
parent ca6fa036f6
commit d8273a15c3
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2 changed files with 27 additions and 3 deletions
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7
nmigen/lib/fifo.py
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@ -369,7 +369,7 @@ class AsyncFIFO(Elaboratable, FIFOInterface):
produce_dec = m.submodules.produce_dec = \
GrayDecoder(self._ctr_bits)
m.d.comb += produce_dec.i.eq(produce_r_gry),
m.d[self._r_domain] += produce_r_bin.eq(produce_dec.o)
m.d.comb += produce_r_bin.eq(produce_dec.o)
w_full = Signal()
r_empty = Signal()
@ -381,7 +381,7 @@ class AsyncFIFO(Elaboratable, FIFOInterface):
]
m.d[self._w_domain] += self.w_level.eq((produce_w_bin - consume_w_bin)[:self._ctr_bits-1])
m.d[self._r_domain] += self.r_level.eq((produce_r_bin - consume_r_bin)[:self._ctr_bits-1])
m.d.comb += self.r_level.eq((produce_r_bin - consume_r_bin)[:self._ctr_bits-1])
storage = Memory(width=self.width, depth=self.depth)
w_port = m.submodules.w_port = storage.write_port(domain=self._w_domain)
@ -509,12 +509,13 @@ class AsyncFIFOBuffered(Elaboratable, FIFOInterface):
self.w_level.eq(fifo.w_level),
]
m.d[self._r_domain] += self.r_level.eq(fifo.r_level + self.r_rdy - self.r_en)
with m.If(self.r_en | ~self.r_rdy):
m.d[self._r_domain] += [
self.r_data.eq(fifo.r_data),
self.r_rdy.eq(fifo.r_rdy),
self.r_rst.eq(fifo.r_rst),
self.r_level.eq(fifo.r_level),
]
m.d.comb += [
fifo.r_en.eq(1)