back.{rtlil,verilog}: deprecate implicit ports.

Fixes #630.
2021-12-13 06:02:29 -06:00 · 2021-12-13 06:02:29 -06:00 · d83c4a1b21
commit d83c4a1b21
parent 24c4da2b2f
3 changed files with 18 additions and 5 deletions
--- a/tests/utils.py
+++ b/tests/utils.py
@ -71,7 +71,7 @@ class FHDLTestCase(unittest.TestCase):
            mode=mode,
            depth=depth,
            script=script,
-            rtlil=rtlil.convert(Fragment.get(spec, platform="formal"))
+            rtlil=rtlil.convert(Fragment.get(spec, platform="formal"), ports=())
        )
        with subprocess.Popen(
                [require_tool("sby"), "-f", "-d", spec_name],