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back.rtlil: implement remaining format specifiers.

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This requires a Yosys version from git. The requirement should be bumped
to a proper release before Amaranth 0.5.
This commit is contained in:
Catherine 2024-03-28 23:42:44 +00:00
parent d3c5b958d3
commit d94c97981a
5 changed files with 160 additions and 27 deletions
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39
amaranth/back/rtlil.py
View file

@ -1090,35 +1090,42 @@ class ModuleEmitter:
args += chunk.value
if type is None:
type = "d"
if type == "x" or type == "X":
# TODO(yosys): "H" type
elif type == "x":
type = "h"
if type == "s":
# TODO(yosys): support for single unicode character?
elif type == "X":
type = "H"
elif type == "c":
type = "U"
elif type == "s":
type = "c"
width = spec["width"]
align = spec["align"]
if align is None:
align = ">" if type != "c" else "<"
if align == "=":
# TODO(yosys): "=" alignment
align = ">"
align = "<" if type in ("c", "U") else ">"
fill = spec["fill"]
if fill not in (" ", "0"):
# TODO(yosys): arbitrary fill
fill = " "
# TODO(yosys): support for options, grouping
if fill is None:
fill = ' '
if ord(fill) >= 0x80:
raise NotImplementedError(f"non-ASCII fill character {fill!r} is not supported in RTLIL")
sign = spec["sign"]
if sign != "+":
# TODO(yosys): support " " sign
if sign is None:
sign = ""
if type == "c":
if type in ("c", "U"):
signed = ""
elif chunk.signed:
signed = "s"
else:
signed = "u"
format.append(f"{{{len(chunk.value)}:{align}{fill}{width or ''}{type}{sign}{signed}}}")
show_base = "#" if spec["show_base"] and type != "d" else ""
grouping = spec["grouping"] or ""
if type == "U":
if align != "<" and width != 0:
format.append(fill * (width - 1))
format.append(f"{{{len(chunk.value)}:U}}")
if align == "<" and width != 0:
format.append(fill * (width - 1))
else:
format.append(f"{{{len(chunk.value)}:{align}{fill}{width or ''}{type}{sign}{show_base}{grouping}{signed}}}")
ports = {
"EN": self.sigspec(cell.en),
"ARGS": self.sigspec(_nir.Value(args)),

2
amaranth/back/verilog.py
View file

@ -9,7 +9,7 @@ __all__ = ["YosysError", "convert", "convert_fragment"]
def _convert_rtlil_text(rtlil_text, *, strip_internal_attrs=False, write_verilog_opts=()):
# This version requirement needs to be synchronized with the one in pyproject.toml!
yosys = find_yosys(lambda ver: ver >= (0, 38))
yosys = find_yosys(lambda ver: ver >= (0, 39, 0, 165))
script = []
script.append(f"read_ilang <<rtlil\n{rtlil_text}\nrtlil")