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build,vendor: never carry around parts of differential signals.

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When a port component is skipped, it should appear neither in the RTL
nor in the constraint file. However, passing around components of
differential ports explicitly makes that harder.

Fixes #456.
Supersedes #457.

Co-authored-by: Jean THOMAS <git0@pub.jeanthomas.me>
This commit is contained in:
whitequark 2020-07-31 13:17:39 +00:00
parent c9662c5ff8
commit d964ba9cc4
10 changed files with 180 additions and 160 deletions
Download patch file Download diff file Expand all files Collapse all files

19
nmigen/build/plat.py
View file

@ -148,16 +148,15 @@ class Platform(ResourceManager, metaclass=ABCMeta):
if pin.dir == "io":
add_pin_fragment(pin, self.get_input_output(pin, port, attrs, invert))
for pin, p_port, n_port, attrs, invert in self.iter_differential_pins():
for pin, port, attrs, invert in self.iter_differential_pins():
if pin.dir == "i":
add_pin_fragment(pin, self.get_diff_input(pin, p_port, n_port, attrs, invert))
add_pin_fragment(pin, self.get_diff_input(pin, port, attrs, invert))
if pin.dir == "o":
add_pin_fragment(pin, self.get_diff_output(pin, p_port, n_port, attrs, invert))
add_pin_fragment(pin, self.get_diff_output(pin, port, attrs, invert))
if pin.dir == "oe":
add_pin_fragment(pin, self.get_diff_tristate(pin, p_port, n_port, attrs, invert))
add_pin_fragment(pin, self.get_diff_tristate(pin, port, attrs, invert))
if pin.dir == "io":
add_pin_fragment(pin,
self.get_diff_input_output(pin, p_port, n_port, attrs, invert))
add_pin_fragment(pin, self.get_diff_input_output(pin, port, attrs, invert))
fragment._propagate_ports(ports=self.iter_ports(), all_undef_as_ports=False)
return self.toolchain_prepare(fragment, name, **kwargs)
@ -239,19 +238,19 @@ class Platform(ResourceManager, metaclass=ABCMeta):
m.d.comb += pin.i.eq(self._invert_if(invert, port))
return m
def get_diff_input(self, pin, p_port, n_port, attrs, invert):
def get_diff_input(self, pin, port, attrs, invert):
self._check_feature("differential input", pin, attrs,
valid_xdrs=(), valid_attrs=None)
def get_diff_output(self, pin, p_port, n_port, attrs, invert):
def get_diff_output(self, pin, port, attrs, invert):
self._check_feature("differential output", pin, attrs,
valid_xdrs=(), valid_attrs=None)
def get_diff_tristate(self, pin, p_port, n_port, attrs, invert):
def get_diff_tristate(self, pin, port, attrs, invert):
self._check_feature("differential tristate", pin, attrs,
valid_xdrs=(), valid_attrs=None)
def get_diff_input_output(self, pin, p_port, n_port, attrs, invert):
def get_diff_input_output(self, pin, port, attrs, invert):
self._check_feature("differential input/output", pin, attrs,
valid_xdrs=(), valid_attrs=None)

16
nmigen/build/res.py
View file

@ -128,9 +128,15 @@ class ResourceManager:
phys_names = phys.names
port = Record([("io", len(phys))], name=name)
if isinstance(phys, DiffPairs):
phys_names = phys.p.names + phys.n.names
port = Record([("p", len(phys)),
("n", len(phys))], name=name)
phys_names = []
record_fields = []
if not self.should_skip_port_component(None, attrs, "p"):
phys_names += phys.p.names
record_fields.append(("p", len(phys)))
if not self.should_skip_port_component(None, attrs, "n"):
phys_names += phys.n.names
record_fields.append(("n", len(phys)))
port = Record(record_fields, name=name)
if dir == "-":
pin = None
else:
@ -166,14 +172,14 @@ class ResourceManager:
if pin is None:
continue
if isinstance(res.ios[0], Pins):
yield pin, port.io, attrs, res.ios[0].invert
yield pin, port, attrs, res.ios[0].invert
def iter_differential_pins(self):
for res, pin, port, attrs in self._ports:
if pin is None:
continue
if isinstance(res.ios[0], DiffPairs):
yield pin, port.p, port.n, attrs, res.ios[0].invert
yield pin, port, attrs, res.ios[0].invert
def should_skip_port_component(self, port, attrs, component):
return False